Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping


In this paper, an iterative technology mapping tool called IMap is presented. It supports depth-oriented (area is a secondary objective), area-oriented (depth is a secondary objective), and duplication-free mapping modes. The edge delay model, as opposed to the more common unit delay model, is used throughout. Two new heuristics are used to obtain area reductions over previously published methods. The first heuristic predicts the effects of various mapping decisions on the area of the final solution and the second heuristic bounds the depth of the mapping solution at each node. In depth-oriented mode, when targeting 5-LUTs, IMap obtains depth optimal solutions that are 13.3% and 12.5% smaller than those produced by CutMAP and FlowMAP-r0, respectively. Targetting the same LUT size in area-oriented mode, IMap obtains solutions that are 13.7% smaller than those produced by duplication-free mapping.


V. Manohararajah, Stephen D. Brown, and Z. Vranesic. "Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping". In Proceedings of the International Workshop on Logic and Synthesis, Temecula, California, USA, June 2004, pp. 14-21.

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