Timing-Driven Functional Decomposition for FPGAs
This work explores the effect of adding a timing driven functional
decomposition step to the traditional field programmable gate
array (FPGA) CAD flow. Once placement has completed, alternative
decompositions of the logic on the critical path are examined for
potential delay improvements. The placed circuit is then modified to use
the best decompositions found. Any placement illegalities introduced by
the new decompositions are resolved by an incremental placement step.
Experiments conducted on Altera's Stratix and Stratix II device families
indicate that this functional decomposition technique can provide
average performance improvements of 6.1% and 5.6% on a large set of
industrial designs, respectively.
Valavan Manohararajah, Deshanand P. Singh, and Stephen D. Brown, "Timing-Driven Functional Decomposition for FPGAs", in Proceedings of the International Workshop on Logic and Synthesis, Lake Arrowhead, CA, June 2005, pp. 415-422.
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