Modular Partitioning for Incremental Compilation
This paper presents an automated partitioning strategy to divide a
design into a set of partitions based on design hierarchy information.
While the primary objective is to use these partitions in an
Incremental Design flow for compile time reduction, the performance
of the partitioned design should not be degraded after partitioning.
Experimental results using the incremental design feature
of Quartus CAD tool from Altera show that our algorithm can
generate partitioning solutions comparable with a set of manually
partitioned real industrial circuits and results in more than 50%
compile time reduction.
Mehrdad Eslami Dehkordi, Stephen D. Brown, Terry Borer, "Modular Partitioning for Incremental Compilation", In Proceedings of the Conference on Field Programmable Logic and Applications, Madrid, Spain, August 2006, pp. 113-118.
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