Experiences with Soft-Core Processor Design


Soft-core processors exploit the flexibility of Field Programmable Gate Arrays (FPGAs) to allow a system designer to customize the processor to the needs of a target application. This paper describes the UT Nios implementation of Altera's Nios architecture. A benchmark set appropriate for soft-core processors is defined. Using the benchmark set, the performance of UT Nios is explored and compared with the commercial implementation.


Franjo Plavec, Blair Fort, Zvonko Vranesic, and Stephen D. Brown, "Experiences with Soft-Core Processor Design," 12th Reconfigurable Architectures Workshop (RAW 2005), Denver, CO, April 2005, pp. 167-170.

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