FPGA Logic Synthesis using Quantified Boolean Satisfiability


This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit and describes how this problem can be formalized and solved using Quantified Boolean Satisfiability. This technique is general enough to be applied to any type of logic function and programmable circuit; thus, it has many applications to FPGAs. The applications demonstrated in this paper include FPGA technology mapping and resynthesis where their results show significant FPGA performance improvements.


A.C. Ling, D.P.Singh, and Stephen D. Brown, "FPGA Logic Synthesis using Quantified Boolean Satisfiability", in SAT '05: The 7th International Conference on Theory and Applications of Satisfiability Testing, St. Andrews, Scotland, June 2005, pp. 444-450.

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