An Area-Efficient Timing Closure Technique for FPGAs using Shannon's Expansion
This paper presents a technique to optimize the speed performance of
circuits implemented in FPGAs. After synthesis, technology
mapping and placement are complete, we apply Shannons expansion to the
most critical sections of the circuit. This approach allows us
to precompute the values of functions that depend on late-arriving
critical signals and use a multiplexer to quickly select the
value when the signal arrives. Any new logic elements created by this
technique are incrementally placed in a minimally disruptive fashion
to ensure convergence between the circuit optimization and the netlist
placement. Experimental results show that this technique can
improve the performance of circuits by 11% on average, and up to 30%
in some cases.
Deshanand P. Singh and Stephen D. Brown, "An Area-Efficient Timing Closure Technique for FPGAs using Shannon's Expansion," The Integration, VLSI Journal special issue on VLSI System-On-Chip, pp. 41-50, 2003.
(Download Full Paper)