Predicting Interconnect Delay for Physical Synthesis in an FPGA CAD Flow


This paper studies the difficulty of predicting interconnect delay in an industrial setting. Industrial circuits and two industrial FPGA architectures were used in the study. We show that there is a large amount of inherent randomness in a state-of-the-art FPGA placement algorithm. Thus, it is impossible to predict interconnect delay with a high degree of accuracy. Futhermore, we show that a simple timing model can be used to predict some aspects of interconnect timing with just as much accuracy as predictions obtained by running the placement tool itself. Next, we present a metric for predicting the accuracy of our interconnect delay model and show how this metric can be used to improve a timing driven physical synthesis flow. Finally, we examine the benefits of using the simple timing model in a timing driven physical synthesis flow, and attempt to establish an upper bound on these possible gains, given the difficulty of interconnect delay prediction.


Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, and Stephen D. Brown, "Predicting Interconnect Delay for Physical Synthesis in an FPGA CAD Flow", IEEE Transactions on Very Large Scale Integration Systems, Volume 15, Number 8, August 2007, pp. 895-903

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