An Area-Efficient Timing-Closure Technique for FPGAs using Shannon.s Expansion
This paper presents a technique to optimize the speed performance of
circuits implemented in FPGAs. After synthesis, technology mapping
and placement are complete, we apply Shannon's expansion to the
most critical sections of the circuit. This approach allows us to
precompute the values of functions that depend on late-arriving critical
signals and use a multiplexer to quickly select the appropriate value
when the signal arrives. Any new logic elements created by this
technique are incrementally placed in a minimally disruptive fashion
to ensure convergence between the circuit optimization and the netlist
placement. Experimental results show that this technique can improve the
performance of circuits by 11% on average, and up to 30% in some cases.
Deshanand Singh and Stephen D. Brown, "An Area-Efficient Timing-Closure Technique for FPGAs using Shannon.s Expansion," International Conference on VLSI, Las Vegas, NV, February 2003.
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