Desktop computers are increasingly used for DSP, multi-media, and data visualization applications. These codes contain a high degree of loop level parallelism, which cannot be fully exploited by superscalar processors. Vector architectures are a viable alternative for increasing workstation performance.
Vector architectures require more compiler support to exploit the available parallelism in a program than superscalar architectures do. Development effort thus shifts from hardware to compiler design.
This thesis describes the development of a vectorizing compiler, implemented in SUIF, capable of targeting a wide variety of vector architectures. The development of a code generator for the T0 vector-microprocessor is also discussed. Performance of T0-like vector processors on a set of multimedia and data-filter applications is also shown to demonstrate the effectiveness of the compiler and to show the applicability of vector architectures to multi-media applications and other common work loads.