Excerpts from EE Times article
by Anthony Cataldo and Loring Wirbel, 11 May 98
Motorola and IBM Split On Direction for PowerPC

Editor's Note: Highlighted emphasis are mine.
Motorola's new Networking and Computer Systems Group chose the recent NetWorld+Interop '98 in Las Vegas to reveal the first major extension to the PowerPC instruction set -- and the first major rift in the PowerPC architectural family.

But the G4-class part from IBM Microelectronics, shown at an Apple conference earlier this year, does not support AltiVec. The difference raises profound questions about the divergence of Motorola and IBM, its partner in the Somerset, N.Y., design center and Apple's traditional second source on PowerPC processors.

"We have participated in the discussions about the [AltiVec] extensions," an IBM spokesman said, "but we made a business decision not to offer them. We believe our customers are better served by a rapid increase in clock frequency than by a more complex instruction set."

[Motorola is positioning] the AltiVec G4 not as a continuing part of Apple's processor road map, but as an attack on the emerging high-end digital signal processing market. Motorola will pitch the chip for access multiplexers, base-station controllers, and similar applications where it would compete against Texas Instruments' 320C6X family, the Analog Devices Sharc processor, and Lucent Microelectronics' 16000 DSP.

The device thus straddles Motorola's DSP and PowerPC families. "We no longer have DSP or Power PC divisions. The [Semiconductor Products] Sector is organized along vertical solutions now," said Phil Grove, director of market development in the Networking and Computer Systems Group.

Grove described fitting the new processor, which has been under development for two years, into Motorola's new solutions strategy. "Trying to make a trade-off between DSP and complex RISC [reduced instruction-set computer] is very difficult," Grove said, "and we tried to avoid making it a battle of architectures. But there are a lot more things you can do in extensible architectures with a multichannel RISC with vector instructions than with DSP."

Grove said the AltiVec PowerPC would be used in applications that required high-bandwidth processing of multiple simultaneous data streams. Motorola sees the existing 24-bit Onyx DSP core being used in single-channel client applications such as cellular-phone codecs and analog modems.

After evaluating both SIMD and very long instruction word (VLIW) schemes, Motorola concluded SIMD was a better fit with its architecture and would make it easier to maintain software compatibility. "VLIW is difficult to program, and is a very different approach than the superscalar RISC PowerPC architecture," Fuller said. By permitting the superscalar CPU to dispatch both conventional PowerPC instructions and AltiVec instructions in the same cycle, Motorola can use the same hardware to compute operand addresses, load and store registers, and perform vector operations.

"In effect, we've already solved the dispatch problem VLIW attempted to solve," Fuller said.

Motorola, of course, has considerable leverage for driving AltiVec into the communications infrastructure. But the architecture's future at Apple is a more open question.

One analyst speculated Apple would ultimately offer under separate sub-brands both systems with fast IBM PowerPC processors and Macintoshes using the Motorola AltiVec parts. What is yet to be determined is which of the two would be the premium brand.


Last Updated: 11 May 1998 by Corinna G. Lee (corinna@eecg.toronto.edu)