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Academic.Research

My research interests, activities and publications

Microprocessor

Research Interests

My research interests lie mostly in these specific areas of Computer Architecture, Compiler Design and Parallelism:
 

  • Traditional software parallelism
  • Pipeline parallelism
  • Automatic parallelization
  • Transactional Memory (TM)
  • Fast synchronization techniques
  • Chip multiprocessor (CMP) architectures

Current.Research

Note: Presentations in non-PDF format are quite large

My.Publications

JudoSTM: A Dynamic Binary Rewriting Approach to Software Transactional Memory  See more...

Marek Olszewski, Jeremy Cutler, and J. Gregory Steffan

Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT), Brasov, Romania, September 2007.

Abstract Collapse Abstract

With the advent of chip-multiprocessors, we are faced with the challenge of parallelizing performance-critical software. Transactional memory (TM) has emerged as a promising programming model allowing programmers to focus on parallelism rather than maintaining correctness and avoiding deadlock. Many implementations of hardware, software, and hybrid support for TM have been proposed; of these, software-only implementations (STMs) are especially compelling since they can be used with current commodity hardware. However, in addition to higher overheads, many existing STM systems are limited to either managed languages or intrusive APIs. Furthermore, transactions in STMs cannot normally contain calls to unobservable code such as shared libraries or system calls.

In this paper we present JudoSTM, a novel dynamic binary-rewriting approach to implementing STM that supports C and C++ code. Furthermore, by using value-based conflict detection, JudoSTM additionally supports the transactional execution of both (i) irreversible system calls and (ii) library functions that may contain locks. We significantly lower overhead through several novel optimizations that improve the quality of rewritten code and reduce the cost of conflict detection and buffering. We show that our approach performs comparably to Rochester's RSTM library-based implementation—demonstrating that a dynamic binary-rewriting approach to implementing STM is an interesting alternative.

Past.Projects

Note: Presentations in non-PDF format are quite large
  • Optimization for Parallelism and Locality - ECE1754 Spring '07
  • Parallelizing FPGA Circuit Placement (VPR) - ECE1755 Fall '06
    • Paper PDF
    • Presentation OpenOffice.org 2.0 Presentation PDF
  • Validation and Analysis of the Caching Address Tags Technique - ECE1773 Fall '06
    • Paper PDF
    • Presentation OpenOffice.org 2.0 Presentation PDF