Tomasz S. Czajkowski

Journals

T.S. Czajkowski and S.D. Brown, Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs, Proceedings of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, Issue 12, December 2008, pp. 2236-2249.

Conference Papers

T.S. Czajkowski and S.D. Brown, Fast Toggle Rate Computation for FPGA Circuits, Proceedings of 18th International Conference of Field-Programmable Logic, Heidelberg, Germany, September 8-10, 2008, pp. 65-70.
T.S. Czajkowski and S.D. Brown, Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs, IEEE Proceedings of the 45th Design Automation Conference, Anaheim, California, June 8-13, 2008, pp. 18-23.
T.S. Czajkowski and S.D. Brown, Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits, IEEE Proceedings of the 44th Design Automation Conference, San Diego, California, June 4-8, 2007, pp. 324-329. (Citation: ACM Digital Library, IEEExplore)
T.S. Czajkowski and J. Rose, A Synthesis Oriented Omniscient Manual Editor, Proceedings of the 12th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, California, February 22-24, 2004, pp. 89-98. (Citation: ACM Digital Library)

The above publications are the author's version of the work. They are posted here by permission of their respective copyright owners for personal use only. The papers posted here are not intended for distribution. The definitive version of each paper was published in the above specified conference proceedings. For your convenience a citation link to the IEEExplore or the ACM Digital Library is provided.

Theses

T. S. Czajkowski, Physical Synthesis Toolkit for Area and Power Optimization on FPGAs, Doctor of Philosophy Thesis Dissertation, Graduate Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario, Canada, 2008.
T. S. Czajkowski, A Synthesis Oriented Omniscient Manual Editor for FPGA Circuit Design, Master of Applied Science thesis, Graduate Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario, Canada, 2004.

Reports

T.S. Czajkowski, B. Fort and I. Kuon, Quake Server Parallelization, Parallel Programming Course Project Report, December 2004.
F. Plavec and T. S. Czajkowski, Distributed File Replication System based on FreePastry DHT, Distributed Systems Course Project Report, December 2004.
T. S. Czajkowski, C. J. Comis, and M. Kawokgy, Fast Fourier Transform Implementation for High Speed Astrophysics Applications on FPGAs, VLSI Systems Project Report, June 2004.

Talks Given

Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs, Design Automation Conference, Anaheim, California, USA, June 10, 2008.
"Functionally Linear Decomposition and Synthesis," University of Waterloo, Waterloo, Canada, January 16, 2008.
"Functionally Linear Decomposition and Synthesis," Xilinx Incorporated, December 6, 2007.
"Functionally Linear Decomposition and Synthesis," University of Toronto, Toronto, Canada, November 22, 2007.
"Functionally Linear Decomposition and Synthesis," Altera Corporation, August 3, 2007.
Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits, Design Automation Conference, San Diego, California, USA, June 6, 2007.
Glitch Reduction for Altera Stratix II Devices, Altera Corporation, March 28, 2007.

Tomasz Sebastian Czajkowski

Ph. D.

Publications