Research Information

Topic: Physical Synthesis for Area and Power Optimization on FPGAs

Supervisor: Professor Stephen D. Brown


Many electronic devices rely on programmable devices to implement their core functionality. For this purpose many designers use Field-Programmable Gate Arrays (FPGAs). When implementing their designs on FPGAs, designers focus on reducing size and improving the speed of their design. Reducing the size allows them to use smaller and less expensive FPGAs, while improving the speed makes the design much more attractive and profitable. Computer Aided Design (CAD) tools that can automatically reduce design size and/or increase its speed are in great demand.

The purpose of this research was to create a CAD tool that facilitates the exploration of area, power and speed optimization techniques. The key feature of this CAD tool is its ability to automatically apply changes to a design on a commercial FPGA/CPLD. While CAD tools such as the work of Czajkowski and Rose [1] and Sentovich et al. [2] provide a similar functionality, the work in [1] is designed for manual optimization of small circuits and the work in [2] targets FPGA architectures that are not nearly as complex as modern FPGAs such as Altera Stratix or Stratix II [3].

In this research we developed a CAD tool, called Physical Synthesis Toolkit (PST), that targets modern commercial FPGA architectures and facilitates research of new area, power and speed optimization techniques for these architectures. This work was completed in two phases: first we created a new CAD software to facilitate access to commercial FPGAs. In this work we provided support for two devices, Altera Stratix and Altera Stratix II via the Quartus II University Interface Program (QUIP) [3]. In this software we support the full range of logic resources, including memory blocks, digital signal processing blocks and I/Os.

The second phase of our research involved the development of area and power optimizations. In our work we have provided three contributions in this context:

  • FLDS - a new logic decomposition and synthesis technique that reduces the area of XOR-based logic circuits by 25.3% as compared to ABC, and 18.8% as compared to BDS-PGA 2.0.
  • Glitch reduction - a power reduction method that utilizes negative edge triggered FFs to remove glitches in a circuit. This optimization was successfully implemented on the Altera Stratix II, and the power savings measured by Altera Quartus II Power Play Power Analyzer showed an average 7% power reduction, with some circuits reaching 25% power reduction.
  • Toggle Rate prediction - a fast toggle rate estimation technique that can determine the power dissipated by each net in a circuit.
Please refer to the "Publications" section of my website for more details on each topic.


[1]    T. S. Czajkowski and J. Rose, "A Synthesis Oriented Omniscient Manual Editor," Proc. of ACM/SIGDA Int. Conference on FPGAs, Monterey, California, Feb 22-24, 2004, pp. 89-98.

[2]    E. M. Sentovich, et al. "SIS: A system for sequential circuit synthesis," Report M92/41, Univ. of California, Berkeley, 1992.

[3]    Altera Corp., Literature, Online:, Oct 5, 2004.