Many electronic devices rely on programmable devices to implement their core functionality. For this purpose many designers use Field-Programmable Gate Arrays (FPGAs). When implementing their designs on FPGAs, designers focus on reducing size and improving the speed of their design. Reducing the size allows them to use smaller and less expensive FPGAs, while improving the speed makes the design much more attractive and profitable. Computer Aided Design (CAD) tools that can automatically reduce design size and/or increase its speed are in great demand.
The purpose of this research was to create a CAD tool that facilitates the exploration of area, power and speed optimization techniques. The key feature of this CAD tool is its ability to automatically apply changes to a design on a commercial FPGA/CPLD. While CAD tools such as the work of Czajkowski and Rose  and Sentovich et al.  provide a similar functionality, the work in  is designed for manual optimization of small circuits and the work in  targets FPGA architectures that are not nearly as complex as modern FPGAs such as Altera Stratix or Stratix II .
In this research we developed a CAD tool, called Physical Synthesis Toolkit (PST), that targets modern commercial FPGA architectures and facilitates research of new area, power and speed optimization techniques for these architectures. This work was completed in two phases: first we created a new CAD software to facilitate access to commercial FPGAs. In this work we provided support for two devices, Altera Stratix and Altera Stratix II via the Quartus II University Interface Program (QUIP) . In this software we support the full range of logic resources, including memory blocks, digital signal processing blocks and I/Os.
The second phase of our research involved the development of area and power optimizations. In our work we have provided three contributions in this context:
 T. S. Czajkowski and J. Rose, "A Synthesis Oriented Omniscient Manual Editor," Proc. of ACM/SIGDA Int. Conference on FPGAs, Monterey, California, Feb 22-24, 2004, pp. 89-98.
 E. M. Sentovich, et al. "SIS: A system for sequential circuit synthesis," Report M92/41, Univ. of California, Berkeley, 1992.
 Altera Corp., Literature, Online: www.altera.com, Oct 5, 2004.