ECE 1767: Project Overview

Spring 2001

In Phase I you will build a parser that reads ISCAS'85 combinational circuits and ISCAS'89 sequential circuits. This phase includes reading the input files into a linked-list data structure, arranging the fan-in/outs of the different gates, and entering buffers in branches. You will also write code for a hash-table that helps speed-up gate searching. (3 weeks)

In Phase II you will add a procedure that levelizes the circuit and you will also build the logic (circuit) simulator and a random test-vector generator. (2 weeks)

Phase III involves the coding of a parallel fault simulator for combinational and sequential circuits. In detail, you will first write the code for a procedure that inserts all possible stuck-at faults in the circuit and performs fault collapsing. Next, you will build a parallel fault simulator and use it (with the random test-vectors) to obtain statistics on the number of faults detected. (3 weeks)

During the last Phase IV of the project, you will add to your program code that implements the PODEM Automated Test Pattern Generator for combinational circuits. This is a procedure that targets a specific stuck-at fault and generates test vectors for the fault. Once the test vector generator is available, you will use it to derive test vectors for a specific stuck-at fault and you will run the parallel fault simulator on that vector to detect other faults as well. (3 weeks)

Detailed handouts on the different phases will be provided at the appropriate time and aforementioned phase deadlines are indicative (= tentative) . There is no official deadline for each but students are expexted to complete (program + debug) each phase before they proceed to the next. For more info, consult the newsgroup. Phase I starts immediately!

Last Updated: Jan 12, 2000