ECE 1767: User Interface
Spring 2001
User Interface
This is a description of a simple user interface you need to
include to your program to ease the examination process. At the end
you will also find the project report you will
need to submit during the in-person examination. In the
description that follows, we indicate with a pause
the point where your program should ask for a carriage return
to continue.
The user interface consists of the following
simple Menu that should appear when you
start your program:
- Circuit Parsing. Selecting this option, your program should
ask for the circuit name to be parsed and it should perform all procedures
described in Phase I as well as circuit levelization.
(pause)
- Random Vector Generation. Your program will ask and
generate a number of random vectors. Every time you run this option
a new set of random vectors should be created and the
old set should be deleted. (pause)
- Parallel Fault Simulation. Selecting this option, your
program should first ask for a desired
fault coverage which is a number between
0 and 100, i.e. the percentage of faults to be detected.
Subsequently, it should insert all possible stuck-at faults, perform
fault collapsing and report results (number of faults before and after
fault collapsing) as described in the handout of Phase III
( pause ).
Finally, it will run parallel fault simulation using the random
vectors that have been generated. At the end of each simulation
cycle it should report the number of faults detected during the
current cycle, the number of faults remaining and the current
fault coverage. The procedure should terminate once the requested
fault coverage has been achieved or if it runs out of random vectors.
Upon termination, it should report statistics such as the number
of random vectors used, number of faults detected, and
overall fault coverage. (pause)
- Test Generation. At first, your program should ask
for a desired fault coverage. Next, it should insert all
possible faults, perform fault collapsing and run
interleaving sessions of PODEM and
parallel fault simulation, as described in the handout of
Phase IV (Section 3) until the fault coverage has been
achieved. Upon termination, it should print statistics such as
the fault coverage achieved, the total number of faults detected, the
total number of test vectors generated and run-time results for the
test generation (PODEM) procedure. (pause)
It is left to the students to include simple error messages once
an invalid option ( i.e. run PODEM on a sequential
circuit, etc) has been selected.
Project Report
During the indvidual in-person project examination you will need
to submit a hard copy of your code that includes detailed
comments before each subroutine. You will also need to
submit a report with the following graphs:
- For circuits c499, c1908, c5315, c6288, s420, s1494, s9234 and s35932
the fault coverage vs. the number of vector simulated during parallel
fault simulation.
- For circuits c499, c1908, c5315, c6288 and c7552
fault coverage
vs. number of vectors for (i) stand-alone
parallel fault simulation, and (ii) PODEM followed
by parallel fault simulation on the generated vectors. Use one
graph per circuit.
- For circuits c499, c1908, c5315, c6288 and c7552
fault coverage
vs. CPU time for (i) stand-alone
parallel fault simulation, and (ii) PODEM followed
by parallel fault simulation on the generated vectors. Use one
graph per circuit.
In all cases, have a user-defined fault coverage maximum value for
this graph which is not too low but not too high either. Take into
account that sequential
designs take more time to converge even for small fault coverage
(50 or 60%).
Mark Breakdown
- Phases I and II: 25%
- Phase III combinational: 20%
- Phase III sequential: 20%
- Phase IV: 20%
- Report and documentation: 15%
Last Updated: March 16, 2000