DART: An FPGA-Based Network-on-Chip Simulation Acceleration Engine
DART is an FPGA implementation of a network-on-chip simulator, where the topology and parameters of the simulated network can be modified without rebuilding the FPGA image. DART is described in our NOCS 2011 paper and is available for download.
DistCL: A Framework for Distributed Execution of OpenCL Kernels
DistCL is a novel framework that distributes the execution of OpenCL kernels across a GPU cluster. DistCL makes multiple distributed compute devices appear to be a single compute device. DistCL is described in our MASCOTS 2013 paper and is available for download: DistCL (version 1.0, released August 12, 2013).
Power Modeling for Heterogeneous Processors
This microbenchmark framework was used in the design of the heterogeneous power model described in our GPGPU 2014 paper and is available for download: Microbenchmarks (version 1.0, releated April 11, 2014).
SynFull: Synthetic Traffic Models Capturing Cache Coherent Behaviour
SynFull is a traffic generation methodology that captures both application and cache coherence behaviour to rapidly evaluate NoCs. SynFull allows designers to quickly indulge in detailed performance simulations without the cost of long-running full system simulation. The model generated and explored in our ISCA 2014 paper is available for download. (version 1.0, released May 14, 2014)