ECE1749H - Interconnection Networks for Parallel Computer Architectures

Spring 2011
Department of Electrical and Computer Engineering
University of Toronto

Instructor:
Prof. Natalie Enright Jerger


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Instructors:

Prof. Natalie Enright Jerger

PT374A (Pratt Buidling), Tel: 978-5056, Email: enright at eecg dot toronto dot edu

Communication: Use e-mail as much as possible, Subject should start with "OCN:"
Office hours: Stop by if door is open or make an appointment by email

Course Description. Interconnection networks form the communication backbone of computers at a variety of scales, from the internet to on-chip networks in multi-core/many-core architectures. With growing emphasis on parallelism as a means of extracting additional processor performance, the communication substrate is a critical factor in both the performance and power consumption of many-core architectures. This course will explore the architecture and design of interconnection networks including topology, routing, flow control and router microarchitecture. This course will also look into the impact on communication requirements of various parallel architectures and cache coherence mechanisms. This course will focus on interconnection network architectures used in multiprocessor systems and many-core designs with emphasis on recent research innovations in these areas.


Lectures

  • Wed 10-12 BA 4164 (staring Jan 12, 2011)

Evaluation Scheme

   Seminar Presentations 20%
   Critique of assigned readings 35%
   Final Project 45%

Required Textbook:
N. Enright Jerger and L-S. Peh, On-Chip Networks.
Available for free download (within UofT): link.
A papercopy of the book is also available for purchase (e.g. Amazon) but is not required.
Additional Readings:
See course outline for assigned research papers
Supplemental Textbook:
W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks

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Last modified: Wed Jan 12 09:52:33 EST 2011