ECE1749H - Interconnection Networks for Parallel Computer Architectures

Spring 2010
Department of Electrical and Computer Engineering
University of Toronto

Instructor:
Prof. Natalie Enright Jerger
MAIN | COURSE OUTLINE | PROJECT | READINGS

Course Outline

Update: Note regarding presentations - please prepare approximately 30 minute presentations. You may use my laptop (I have Office for Mac and Keynote) or bring your own. If you wish to use my laptop to present, please email me your presentation by 9 am on the day of class.

Update: Presenters added to schedule.
E-mail me if you are enrolled in class but I have not scheduled you to present or if you have a significant conflict with your scheduled presentation (e.g. conference travel).
Note: Outline subject to change

DateTopics Reading Assignment
January 13, 2010 Introduction,
System Interfaces
 Chapter 1
Chapter 2		 --
January 20, 2010 Topology,
Routing
 Chapter 3
Chapter 4		 --
January 27, 2010 Flow Control,
Router Microarchitecture
 Chapter 5[PPT][PDF]
Chapter 6[PPT][PDF]		 --
February 3, 2010 Topology
 1. Flattened Butterfly Topology for On-Chip Networks PDF (Presenter: Robert Hesse)
2. Design and Evaluation of a Hierarchical On-Chip Interconnect
for Next-Generation CMPs PDF (Presenter: Jason Luu)
3. Design Tradeoffs for Tiled CMP On-Chip Networks PDF
4. Cost-Efficient Dragonfly Topology for Large-Scale Systems PDF
 Critiques of 2 Papers due
(see Readings for details)
February 10, 2010 Routing Algorithms
 1. Recursive Partitioning Multicast: A Bandwidth-Efficient Routing for
Networks-on-Chip PDF
2. Region-based Routing: An Efficient routing mechanism to tackle
unreliable hardware in networks on chip PDF (Presenter: )
3. GOAL: A load-balanced adaptive routing algorithm for torus networks PDF
4. Near optimal worst-case throughput routing for two-dimensional mesh
networks PDF
 2 Critiques due
February 24, 2010 Flow Control 1. Express Virtual Channels: Toward the ideal interconnection fabric
PDF (Presenter: Jongsok Choi)
2. ViCHar: A Dynamic Virtual Channel Regulator for Network-on-Chip
Routers PDF (Presenter: Manisha Tatikonda)
3. Elastic-Buffer Flow Control for On-Chip Networks PDF
1 Critique due
Project Proposal due (e-mail)
March 3, 2010 Router Microarchitecture 1. Low-Latency Virtual-Channel Routers for On-Chip
Networks PDF (Presenter: Mark Jeffrey)
2. The Alpha 21364 network architecture PDF
3. Rotary Router: an efficient architecture for CMP interconnection networks PDF
4. Microarchitecture of a High-Radix Router PDF
 2 Critiques due
March 10, 2010
Class cancelled due to conference travel
Tentatively add 1 week at end of term (April 14)
 - - -
March 17, 2010 Systems 1. A 5-GHz Mesh Interconnect for a Teraflops Processor PDF (Presenter: Yuri Sagalov)
2. Characterizing the Cell EIB On-Chip Network PDF
3. On-Chip Interconnection Architecture of the Tile Processor PDF
1 Critique due
March 24, 2010 Power 1. Performance and Power Optimization through Data Compression
in Network-on-Chip Architectures PDF
2. A Gracefully Degrading and Energy-Efficient Modular Router
Architecture for On-Chip Networks PDF (Presenter: Victor Szeto)
3. Power-driven Design of Router Microarchitectures in On-chip
Networks PDF
1 Critique due
Project Progress Report Due (e-mail)
March 31, 2010 Cache Coherence
Quality of Service
Fault Tolerance		 1. In Network Coherence Filters: Snoopy Coherence without
Broadcasts PDF (Presenter: Sam Vafaee)
2. Globally Synchronized Frames for Guaranteed Quality-of-Service
in On-Chip Networks PDF
3. BulletProof: A Defect Tolerant CMP Switch Architecture PDF
 1 Critique Due
April 7, 2010 Emerging Technology (Optics and 3D) 1. A Low-Radix and Low-Diameter 3D Interconnection
Network Design PDF (Presenter: Rizwan Haider)
2. CMP Network-on-Chip Overlaid with Multi-Band RF-Interconnect PDF (Presenter: Mark Teper)
3. Corona: System Implications of Emerging Nanophotonic
Technology PDF
 1 Critique Due
April 14, 2010 Project Presentations
--
Last modified: Tue Mar 2 11:03:59 EST 2010