Complete list of publications. See also: Google Scholar Profile
Book
On-Chip Networks
Natalie Enright Jerger and Li-Shiuan Peh
Refereed Conference and Journal Publications
Performance Analysis of Broadcasting Algorithms on the Intel Single Chip Cloud Computer
John Matienzo and Natalie Enright Jerger
In Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS). April 2013. (to appear)
A Dual-Grain Hit/Miss Detector for Large Stacked-Die DRAM Caches
Michel El Nacouzi, Islam Atta, Myrto Papadopoulou, Jason Zebchuk, Natalie Enright Jerger and Andreas Moshovos
In the Design, Automation and Test in Europe Conference. March 2013. (to appear)
Holistic Routing Algorithm Design to Support Workload Consolidation in NoCs
Sheng Ma, Natalie Enright Jerger, Zhiying Wang, Mingche Lai and Libo Huang
IEEE Transactions on Computers (Preprint)
DART: A Programmable Architecture for NoC Simulation on FPGAs
Danyao Wang, Charles Lo, Jasmina Vasiljevic, Natalie Enright Jerger and J. Gregory Steffan
IEEE Transactions on Computers (Preprint [PDF])
Fine-Grained Bandwidth Adaptivity in Networks-on-Chip Using Bidirectional Channels
Robert Hesse, Jeff Nicholls and Natalie Enright Jerger
In Proceedings of the 6th International Symposium on Networks-on-Chip. May 2012. [PDF]
Moths: Mobile Threads for On-Chip Networks
Matthew Misler and Natalie Enright Jerger
ACM Transactions on Embedded Computing (to appear)
Supporting Efficient Collective Communication in NoCs
Sheng Ma, Natalie Enright Jerger, Zhiying Wang
In Proceedings of the 18th International Symposium on High Performance Computer Architecture. February 2012. [PDF]
Whole Packet Forwarding: Efficient Design of Fully Adaptive Routing Algorithms for Networks-on-Chip
Sheng Ma, Natalie Enright Jerger, Zhiying Wang
In Proceedings of the 18th International Symposium on High Performance Computer Architecture. February 2012. [PDF]
Exploration of Temperature Constraints for Thermal Aware Mapping of 3D Networks on Chip
Parisa Khadem Hamedani, Shaahin Hessabi, Hamid Sarbazi-Azad, Natalie Enright Jerger
In Proceedings of 20th Euromicro International Conference on Parallel, Distributed and Network-Based Processing. February 2012. [PDF]
DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chipISCA '11 Proceeding of the 38th annual international symposium on Computer architecture, 2011
DART: a programmable architecture for NoC simulation on FPGAsNOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, 2011
SigNet: Network-on-Chip Filtering for Coarse Vector Directories
Natalie Enright Jerger
In Proceedings of the Conference on Design, Automation and Test in Europe. March 2010. [PDF][SLIDES]
Abstract Bibtex
SCARAB: a single cycle adaptive routing and bufferless networkMICRO 42 Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, 2009
Achieving predictable performance through better memory controller placement in many-core CMPsISCA '09 Proceedings of the 36th annual international symposium on Computer architecture, 2009
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
Radu Marculescu, Umit Y. Ogras, Li-Shiuan Peh, Natalie Enright Jerger, Yatin Hoskote
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(1), January, 2009. [PDF]
Virtual Tree Coherence: Leveraging Regions and In-Network Multicast Trees for Scalable Cache Coherence
Natalie Enright Jerger, Li-Shiuan Peh, Mikko Lipasti
In Proceedings of the International Symposium on Microarchitecture (MICRO-41), Lake Como Italy, November 2008. (accepted 40/210). [PDF]
Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast SupportISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture, 2008
Circuit-Switched Coherence
Natalie Enright Jerger, Li-Shiuan Peh, Mikko H. Lipasti
In 2nd Annual IEEE Network on Chip Symposium, Newcastle-Upon-Tyne, UK, April 2008.[PDF][PPT]
An Evaluation of Server Consolidation Workloads for Multi-core Designs
Natalie Enright Jerger, Dana Vantrease, Mikko H. Lipasti
In Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), Boston MA, September 2007. [PDF][PPT]
Circuit-Switched Coherence
Natalie Enright Jerger, Mikko H. Lipasti, Li-Shiuan Peh
In IEEE Computer Architecture Letters, vol. 6, no. 1, Jan-Jun, 2007. [PDF]
Women and Girls in Science and Engineering: Understanding the Barriers to Recruitment, Retention and Persistence Across the Educational Trajectory.
Elizabeth M. O'Callaghan and Natalie D. Enright Jerger
In Journal of Women and Minorities in Science and Engineering. Volume 12, 2006.
Friendly Fire: Understanding the Effects of Multiprocessor Prefetches
Natalie Enright Jerger, Eric L. Hill, Mikko H. Lipasti
In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2006), Austin, TX, March 2006. [PDF]
Workshop Papers
DART: Fast and Flexible NoC Simulation using FPGAs
Danyao Wang, Natalie Enright Jerger and J. Gregory Steffan
In the 5th Annual Workshop on Architectural Research Prototyping 2010 (held in conjunction with ISCA 2010). [PDF]
PhD Thesis
Chip Multiprocessor Coherence and Interconnect System Design (December 2008)
[PDF][PPT]
US Patent
Natalie D. Enright, Jamison Collins, Perry Wang, Hong Wang, Xinmin Tran, John Shen, Gad Sheaffer, Per Hammarlund.
Mechanism to exploit synchronization overhead to improve multithread performance.
Patent no: 7487502. Sept 2009.