My primary research interests lie in on-chip interconnection networks and cache coherence protocols for many-core architectures.
My current research re-examines and challenges some of the design assumptions that hold true for shared-memory multiprocessors when explored in the context of chip multiprocessors. As we migrate many of these design choices on-chip, it is worthwhile to examine their suitability and present novel solutions that are attractive in the unique environment of a many-core architecture. The goal of this research is to carefully consider communication requirements (as dictated by the coherence protocol), codesign the interconnect to better serve the coherence protocol, and improve the cache coherence protocols to better leverage the functionality of the on-chip interconnection network.
For an overview and introduction to on-chip network research, I refer the interested reader to the Computer Architecture Synthesis Lecture on
On-Chip Networks.
I am also interested in architectural support for operating systems and virtual machines, particularly in light of future many-core architectures.
Server consolidation workloads are an emerging class of workload that can fully leverage the resources provided by many-core architectures; through resource sharing, these workloads have the opportunity for both constructive and destructive interference.
Resource management policies for sharing of architectural resources will be important as we find new ways to utilize the abundant cores and memory on-chip.
I am currently looking for motivated, hard-working students to join my research group. If you have applied to graduate school at University of Toronto and feel your interests align with mine, please email me. You are more likely to receive a response if you can demonstrate that you have read at least one of my papers. E-mails that address me as "Dear Sir:" will be ignored.
Last updated: July 2009