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# A Differential-Pair with Active Loads and Biasing #
# (written in the BALLISTIC analog layout language) #
#####################################################

# generates the layout of a differential-pair connected
# to active loads and a biasing transistor.

# put your own variables here (or anywhere) and optionally
# set processing flags:
DEFAULTS {
	DPWidth = 200
	DPLength = 2*LAMBDA
	PRINT amplifier.ps
	OPTIONS GLOBAL HEIGHT=100
}

# declare all your objects, instances, subcircuits, and
# cells here for later definition:
DECLARATIONS {
	DIFFPAIR qdp
	TRANSISTOR qload qbias
	SUBCIRCUIT xloads
	INSTANCE input load1 load2 loads bias
	CELL amplifier
}

# define the parameters (and generate the layouts) for
# the low-level building-blocks you will need:
BLOCKS {
	qdp	TYPE=N WIDTH=DPWidth LENGTH=DPLength \
		ASPECT=0.5 ORIENT=HOR
	qload	TYPE=P WIDTH=100 UNITWIDTH=20 ASPECT=0.3 \
		ORIENT=VER
	qbias	TYPE=N WIDTH=10 LENGTH=2.4 ORIENT=HOR
}

# create your own subcircuits for hierarchical designs:
SUBCIRCUITS {
	xloads {
		INSTANCE load1 load2 OF qload
		MOVE load2 RIGHTOF load1 SEP=10 FLIP=Y
		WIRE load1.source load2.source WIDTH=20 \
			HTRUNC=YES TTRUNC=Y
		WIRE load1.gate load2.gate
		WIRE load1.gate load1.drain
		EXPORT in1=load1.drain in2=load2.drain
		EXPORT Vdd=load1.source X=(load1.LEFT+load2.RIGHT)/2
	}
}

# define cells and call instances of other cells, other
# subcircuits, and low-level building-blocks here for
# location and wiring (similar to subcircuits):
CELLS {
	amplifier {
		OPTIONS BUS TYPE=LINE SEP=100 WIDTH=10*LAMBDA
		INSTANCE loads OF xloads
		INSTANCE bias OF qbias
		INSTANCE input OF qdp
		MOVE bias ABOVE Gnd
		MOVE loads BELOW Vdd
		MOVE input BELOW loads
		WIRE input.output1 loads.in1
		WIRE input.output2 loads.in2
		WIRE input.source bias.drain SHAPE=VH
		WIRE bias.source Gnd
	}
}