Marcel Gort

Marcel Gort and Jason Anderson. Range and Bitmask Analysis for Hardware Optimization in High-Level Synthesis. Asia and South Pacific Design Automation Conference (ASPDAC), 2013.

Marcel Gort and Jason Anderson. Analytical Placement for Heterogeneous FPGAs. International Conference of Field Programmable Logic and Applications (FPL), 2012.

Marcel Gort and Jason Anderson. Reducing FPGA Routing Run-time through Algorithm and Architecture. International Conference of Field Programmable Logic and Applications (FPL), 2011. [pdf] (Best paper award)

Marcel Gort and Jason Anderson. Deterministic Multi-core parallel routing for FPGAs. In International Conference of Field Programmable Technology (FPT), 2010. [pdf]

Flavio M. De Paula, Marcel Gort, Alan J. Hu, Steve J.E. Wilton, and Jin Yang. Backspace: Formal Analysis for Post Silicon Debug. In Formal Methods in Computer Aided Design, pages 35-44, 2008. [pdf]

Flavio M. De Paula, Marcel Gort, Alan J. Hu, Steve J.E. Wilton, and Jin Yang. Backspace: Moving towards reality. In Workshop on Microprocessor Test and Verification, 2008. [pdf]

Marcel Gort and Jason Anderson. A Combined Architecture/Algorithm Approach to Fast FPGA Routing. to appear in IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2012

Marcel Gort and Jason Anderson. Accelerating FPGA Routing Through Parallelization and Engineering Enhancements. IEEE Transactions on Computer Aided Design for Integrated Circuits and Systems (TCAD), Vol. 31, Issue 1, Jan. 2012

Marcel Gort, Flavio M. De Paula, Johnny J.W. Kuan, Tor M. Aamodt, Alan J. Hu, Steven J.E. Wilton, Jin Yang. Formal-Analysis-Based Trace Computation for Post-Silicon Debug. IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, Vol. 19, Issue 12, Oct. 2011

Flavio M. De Paula, Marcel Gort, Alan J. Hu, Steve J.E. Wilton, and Jin Yang. Formal Analysis to Support Post-Silicon Debugging, SRC Techcon, 2008

Flavio M. De Paula, Marcel Gort, Alan J. Hu, Steve J.E. Wilton, and Jin Yang. Formal Analysis to Support Post-Silicon Debugging, CMC Microsystems Annual Symposium, 2008

Marcel Gort. Reducing FPGA Router Run-Time Through Algorithm and Architecture. University of Toronto FPGA Seminar, September 2011

Marcel Gort. Fast FPGA Routing using PathFinder and SAT. Connections: University of Toronto ECE Graduate Symposium, May 2011

Marcel Gort. Deterministic Multi-core parallel routing for FPGAs. University of Toronto FPGA Seminar, November 2010 [video]

Marcel Gort, S.J.E.Wilton, BackSpace: Formal Analysis for Post-Silicon Debug. System and SoC Debug Integration and Applications - co-located with DAC 2010, Anaheim, CA

Marcel Gort, S.J.E.Wilton, Backspace: Post-Silicon Debug Methodology. Cascadia Workshop 2008, Burnaby, B.C.

Marcel Gort, S.J.E.Wilton, Practical Considerations for BackSpace Debugging. Cascadia Workshop 2009, Seattle, WA

Marcel Gort. Practical Considerations for Post-Silicon Debug using BackSpace, M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of British Columbia [pdf]