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Publications Submitted to Refereed Journals for Review

1. None in review

Refereed Journal Publications

1. Yadollah Eslami, Ali Sheikholeslami, P. G. Gulak, "An Area-Efficient Universal Cryptography Processor for Smart Cards", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 1, January 2006.

2. W. Gross, F. Kschischang, R. Koetter and P. G. Gulak, "Applications of Algebraic Soft-Decision Decoding of Reed-Solomon Codes", IEEE Transactions on Communications. Accepted for publication.

3. W. Gross, F. Kschischang, R. Koetter and P. G. Gulak, “Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Soloman Decoders”, < i>Journal of VLSI Signal Processing, In Press.

4. D. Gnaedig, E. Boutillon, M. Jezequel, V. Gaudet and P. G. Gulak, “On Multiple Slice Turbo Codes”, Annals of Telecommunications, , Vol. 60,
   No.1-2, January/February 2005, pp.79-102.

5. V. Gaudet and P. G. Gulak, "A 13.3Mbps, 0.35um CMOS Analog Turbo Decoder IC with Configurable Interleaver" (invited), IEEE Journal of Solid-State Circuits, Nov.  2003.

6. T. Esmailian, F.R. Kschischang, and P. G. Gulak, “In-Building Power Lines as High Speed Communication Channels:  Channel Characterization and a Test Channel Ensemble”, International Journal of Communication Systems, pp. 381-400, May 2003. (NSERC), Motorola.

7. J. Siu, Y. Eslami, A. Sheikholeslami, P. G. Gu lak, T. Endo, and S. Kawashima, "A Current-Based Reference-Generation Scheme for 1T-1C Ferroelectric Random-Access Memories", IEEE Journal of Solid-State Circuits, Vol. 38, No. 3, March 2003, pp. 541-549.

8. E. Boutillon, W. Gross, and P. G. Gulak, "VLSI Architectures for the MAP Algorithm", IEEE Trans. on Communications, Vol. 51, No. 2, Feb. 2003, pp. 175-185. 

9. V. Gaudet, R. Gaudet and P. G. Gulak, "Programmable Interleaver Design for Analog Iterative Decoders", IEEE Transactions on Circuits and Systems II - Analog and Digital Signal Processing, Vol. 49, No. 7, pp. 457-464, July 2002.

10. W. Gross, V. Gaudet, and P. G. Gulak, “Difference Metric Soft-output Detection:  Architecture and Implementation”, IEEE Transactions on Circuits and Systems II–Analog and Digital Signal Processing, Vol. 48, No. 10, pages 904-911, October 20 01.

11. Sheikholeslami, A., and P. G. Gulak, Takauchi, H., Tamura, H., Yoshioka, H., and Tamura, T.,  "A Pulse-Based, Parallel-Element Macromodel for Ferroelectric Capacitors", IEEE Trans. On Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 47, No. 4, July 2000, pp. 784-791.

12. Sheikholeslami, A., and P. G. Gulak, "A Survey of Circuit Innovations in Ferroelectric Random-Access Memories", Proceedings of  the IEEE. Vol. 88, No. 5, May 2000, pp. 667-689.

13. J. Omidi, P. G. Gulak and S. Pasupathy, “Parallel Structures for Joint Channel Estimation and Data Detection Over Fading Channels”, IEEE Transactions on Selected Areas of Communications  (special issue on Signal Processing and Wireless Communications), Vol. 16, No. 9, pp. 1616-1629, Dec. 1998.

14. Gaudet, V., and P. G. Gulak,  "Implementation Issues for High-Bandwidth Field-Programmable Analog Arrays", Journal of Circuits, Systems, and Computers Special Issue on Analog and Digital Arrays, World Scientific Publishing, Vol. 8, No. 5-6, pages 541-558, 1998.

15. W. Gross and P. G. Gulak, “Simplified MAP Algorithm suitable for implementation of turbo decoders”, Electronics Letters, Aug. 6, 1998, Vol. 34, No. 16, pp. 1577-1578.

16. D. R. D’Mello and P. G. Gulak, “Design Approaches to Field-Programmable Analog Integrated”, (Special Issue on Programmable Analog Systems), Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, Vol. 17, No. 1-2, pp. 7-34, Sept. 1998.    

17. K. Lowe and P. G. Gulak, "A Joint Gate Sizing and Buffer Insertion Method for Optimizing Delay and Power in CMOS and BiCMOS Combina tional Logic", IEEE Transactions on CAD, Vol. 17, No. 5, May 1998, pp. 419-434.

18. K. Schultz and P. G. Gulak, "Physical Performance Limits for Shared Buffer ATM Switches", IEEE Transactions on Communications, Vol. 45, No. 8, pp. 997-1007, Aug. 1997.

19. A. Sheikholeslami and P. G. Gulak, “A Survey of Behavioral Modeling of Ferroelectric Capacitors”, IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, Vol. 44, No. 4, pp. 917-924, July 1997.

20. K. Schultz and P. G. Gulak, "Multicast Contention Resolution with Single-Cycle Windowing Using Content Addressable FIFOs", IEEE/ACM Transactions on Networking, Vol. 4, No. 5, pp. 731-742, Oct. 1996.

21. A. Sheikholeslami and P. G. Gulak, “Transient Modeling of Ferroelectric Capacitors for Semiconductor Memories”, Microelectronic Engineering, Vol. 29, No. 1-4, 1995, pp. 141-144.

22. A. Sheikholeslami and P. G. Gulak, “Transient Modeling of Ferroelectric Capacitors for Nonvolatile Memories”, IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 43, No. 3, 1996, pp. 450-456.

23. K. Schultz and P. G. Gulak, "Fully-Parallel Integrated CAM/RAM Using Pre-Classification to Enable Large Capacities", IEEE Journal of Solid-State Circuits, Vol. 31, No. 5, pp. 689-699, May 1996.

24. K. Schultz and P. G. Gulak, "Architectures for Large-Capacity CAMs", Integration, the VLSI Journal, 18, No. 2-3, pp. 151-171, 1995.

25. K. Schultz and P. G. Gulak, Throttled Buffer Asynchronous Switch for ATM, IEICE Transactions on Communications, (Special Issue on Future Private Networks),Vol. E77-B, No. 3, March 1994, pp. 351-358.

26. G. Feygin, P. G. Gulak and P. Chow, Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding, The Journal of Information Processing and Management (Special Issue on Data Compression), Vol. 30, No. 6, pp. 805-816, Nov-Dec 1994.

27. K.C. Smith and P. G. Gulak, Prospects for Multi-Valued Integrated Circuits (invited paper), IEICE Transactions on Electronics, Vol. E76-C, No. 3, March 1993, pp. 372-382.

28. E. Lee and P. G. Gulak, Current-Mode Multivalued Dynamic MOS Memory with Error Correction, IEE Electronics Letters, Vol. 28, No. 11, May 1992, pp.1067-1069.

29. E. Lee and P. G. Gulak, Field Programmable Analog Array Based on MOSFET Transconductors, IEE Electronics Letters, Vol. 28, No. 1, Jan. 1992, pp. 28-29.

30. G. Feygin, P. G. Gulak and P. Chow, A Multiprocessor Architecture for Viterbi Decoders with Linear Speed-up, IEEE Transactions on Signal Processing, Vol. 41, No. 9, September 1993, pp. 2907 - 2917.

31. J. Erfanian, S. Pasupathy, P. G. Gulak, Reduced Complexity Symbol Detectors with Parallel Structures for ISI Channels, IEEE Trans. on Communications, Vol. 42; No. 2/3/4, Feb/Mar/April, 1994, pp.1661-1671.

32. G. Feygin and P. G. Gulak, Architectural Tradeoffs for Survivor Sequence Memory Management in Viterbi Decoders, IEEE Transactions on Communications, Vol. 41, No. 3, March 1993, pp. 425 - 429.

33. E. Lee and P. G. Gulak, A CMOS Field Programmable Analog Array, IEEE J. of Solid State Circuits, Vol. 26, No. 12, December 1991, pp. 1860-1867.

34. E. Lee and P. G. Gulak, Error Correction Technique for Multivalued MOS Memory, IEE Electronics Letters, Vol. 27, No. 15, July 18, 1991, pp. 1321-1323.

35. P. G. Gulak and T. Kailath, Locally Connected VLSI Architectures for the Viterbi Algorithm, IEEE Journal on Selected Areas in Communications (Special Issue on VLSI in Communications), Vol. 6, No. 3,  April 1988, pp. 527-537.

36. M. Horowitz, P. Chow, M. Wing, D. Stark, R. Simoni, A. Salz, S. Przybylski, J. Hennessy, P. G. Gulak, A. Agarwal, J. Acken, MIPS-X: A 20 MIPS Peak, 32-Bit Microprocessor with On-Chip Cache, IEEE Journal of Solid State Circuits, Vol. SC-22, No. 5, October 1987, pp. 790-799.

37. H.C. Card, P. G. Gulak, R.D. McLeod and W. Pries, (lT) Complexity Measures for VLSI Computations in Constant Chip Area, IEEE Transactions on Computers, Volume C-36, No. 1, January 1987, pp. 112-117.

38. G.E. Bridges, W. Pries, R.D. McLeod, M. Yunik, P. G. Gulak and H.C. Card, Dual Systolic Architectures for VLSI Digital Signal Processing Systems, IEEE Transactions on Computers, Volume C-35, No. 10, October 1986, pp. 916-923.

39. P. G. Gulak and E. Shwedyk, VLSI Structures for Viterbi Receivers:  Part I - General Theory and Applications, IEEE Journal on Selected Areas in Communications (Special Issue on VLSI in Communications), Volume SAC-4, No. 1, January 1986, pp. 142-154.

40. P. G. Gulak and E. Shwedyk, VLSI Structures for Viterbi Receivers:  Part II - Encoded MSK Modulation, IEEE Journal on Selected Areas in Communications (Special Issue on VLSI in Communications), Volume SAC-4, No. 1, January 1986, pp. 155-159.

41. D.A. Buchanan and P. G. Gulak, Photocounting Statistics Associated with Temperature Fluctuations in Semiconductor Lasers, Journal of Applied Optics, Vol. 22, No. 1, January 1, 1983, pp. 37-48.

42. P. G. Gulak, E. Shwedyk and D. Card, An Improved Approximation for the Isolated Transition in Saturated Magnetic Recording, IEEE Transactions on Magnetics,Vol.MAG-18, No. 5, 1982, pp. 989-992.

Refereed Conference Papers

1. M. Shabany, P. G. Gulak, "VLSI Implementation of a Sequential Monte Carlo Receiver", IEEE International Symposium on Circuits and Systems (ISCAS'06), Greece, May 21-24, 2006.

2. M. Shabany, P. G. Gulak, "An Efficient Architecture for Distributed Resampling for High-Speed Particle Filtering",  IEEE International Symposium on Circuits and Systems (ISCAS'06), Greece, May 21-24, 2006.

3. I. Hosseini, M. J. Omidi, K. Kasiri, A. Sadri, P. G. Gulak, "PAPR Reduction in OFDM Systems Using Polynomial-based Compressing and Iterative Expanding", ICASSP 2006, Toulouse, France, May 14-19, 2006.

4. M. Shabany, H. Shojania, J. Zhang, J. Omidi, P. G. Gulak, “VLSI Architecture of a Wireless Channel Estimator Using Sequential Monte Carlo Methods”, IEEE Workshop on Signal Processing Advances in Wireless Communications (SPAWC'05), 2005.

5. H. Zamiri-Jafarian and P.G.Gulak, "Adaptive Channel SVD Estimation for MIMO-OFDM Systems" (Session 5B), IEEE 61st Semiannual Vehicular
   Technology Conference, Stockholm, Sweden, May 30-June 1, 2005.

6. H. Zamiri-Jafarian and P.G.Gulak, "Iterative MIMO Channel SVD Estimation", IEEE International Conference on Communications, Seoul,
   Korea, May 16-20, 2005.

7. W. Gross, F. Kschischang and P. G. Gulak, “An FPGA Interpolation Engine for Soft-Decision Reed-Soloman Decoding”, Proceedings of the 2004 Symposium on Field-Programmable Custom Computing Machines, April 2004.

8. D. Gnaedig, E. Boutillon, M. Jezequel, V. Gaudet, and P. G. Gulak, "On Multiple Slice Turbo Codes", 3rd Int. Symposium on Turbo Codes and Related Topics, Brest, France, Sept. 2003, pp. 343-346.
9. V. Gaudet and P. G. Gulak, "A 13.3Mbps, 0.35um CMOS Analog Turbo Decoder IC with a Configurable Interleaver", 2003 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 148-149, 484, Feb. 2003.
10. W. Gross, F. Kschischang, R. Koetter, and P. G. Gulak, "A VLSI Architecture for Interpolation in Soft-Decision List Decoding of Reed-Solomon Codes", Proc. of the 2002 IEEE Workshop on Signal Processing Systems, SIPS'02, San Diego, Oct. 2002, pp. 39-44.
11. T. Fill and P. G. Gulak, “An Assessment of VLSI and Embedded Software Implementations for Reed Solomon Decoders, IEEE Signal Processing Systems SIPS’02, Oct. 2002, pp. 99-102.
12. K. Pagiamtzis and P. G. Gulak, “Empirical Performance Prediction for IFFT/FFT cores for OFDM Systems-on-a-Chip, IEEE Midwest Symposium on Circuits and Systems, August 2002, Vol. 1, pp. 583-586.
13. W. Gross, F. Kschischang, R. Koetter, and P. G. Gulak, "Simul ation Results for Algebraic Soft-Decision Decoding of Reed-Solomon Codes", Proc. of the 21st Biennial Symposium on Communications, June 2002, Queen's University, Kingston, Canada, pp. 356-360.
14. J. Siu, Y. Eslami, A. Sheikholeslami, P. G. Gulak, T. Endo, and S. Kawashima, “A 16kb 1T1C FeRAM Testchip Using Current-Based Reference Scheme”, IEEE Custom Integrated Circuit Conference, pp. 107-110, May 2002.
15. T. Esmailian, F.R. Kschischang, and P. G. Gulak. “A 32-Point Multiplier-Free Approximate FFT,” Proceedings of the 21st Biennial Symposium on Communications, Queen’s University, June 2002, pp. 448-452.
16. T. Esmailian, F. R. Kschischang, and P. G. Gulak, “An In-Building Power Line Channel Simulator”, Proceedings of the 2002 International Symposium on Power Line Communications and its Applications, ISPLC2002, pp. 31-35, March 2002, Athens, Greece.
17. T. Esmailian, F.R. Kschischang, and P. G. Gulak, “Capacity Distribution of Radiation-Limited In-Building Power Lines”, Proceedings of the 2002 International Symposium on Power Line Communications and its Applications, ISPLC2002, pp. 118-122, March 2002, Athens, Greece.
18. Y. Eslami, J. Siu, A. Sheikholeslami, P. G. Gulak, T. Endo, and S. Kawashima, “A 2T-2C FeRAM Testchip for Optimum Bitline and Cell  Capacitances”, Proc. Of the 1^st Int’l Meeting on Ferroelectric Random Access Memories, pp. 178-179, Nov. 2001.
19. A. Ghazel, E. Boutillon, J.-L. Danger, P. G. Gulak, H. Laamari, “Design and Performance Analysis of a High-Speed AWGN Communications Channel Emulator”, 2001 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Aug. 2001, Volume 2, pp. 374-377.
20. N. Sohi and P. G. Gulak, “A Multi-Standard Set-Top Box Channel Decoder”, IEEE Signal Processing Systems, SIPS’00, Oct. 2000, pp. 295-304.
21. W. Gross, V. Gaudet and P. G. Gulak, “A VLSI Architecture for Soft-output PR4 Detection”, 2000 IEEE Midwest Symposium on Circuits and Systems, August 2000, Vol. 1, pp. 416-419.
22. Boutillon, E., Gross, W., and Gulak, G., "Gestion De La Memoire Pour L'Algorithme Du Forward Backward", 5eme Workshop AAA sur 'Adequation Algorithme Architecture, 26-28 Jan. 2000, INRIA Rocquencourt, France.
23. Esmailian, T., Gulak, G., and Kschischang, F., "A Discrete Multitone Power Line Communications System", IEEE Int. Conference on Acoustics, Speech, and Signal Processing, ICASSP 2000, Istanbul, Turkey, Vol. 5, pp. 2953-2956.
24. Esmailian, T., Kschischang, F., and Gulak, G., "Simulation of a Discrete Multitone System Over In-Building Power Line", 20^th Biennial Symposium on Communications, Queen’s University, May 2000, pp. 32-36.
25. Esmailian, T., Kschischang, F., and Gulak, G., "Characteristics of In-Building Power Lines at High Frequencies and their Channel Capacity", Proceedings of 2000 Int. Symposium on Power-Line Communications and its Applications, pp. 52-59, ISPLC 2000, Limerick, Ireland.
26. J. Podaima and P. G. Gulak, "Self-Timed Fully Parallel Content Addressable Queue for Switching Applications, CICC, pp. 239-242, May 1999, paper 11.4.
27. A.H. Banihasherni, Frank, R. Kschischang, P. G. Gulak, "On Tanner Graphs of Lattices and Codes", Information Theory, Proceedings, 1998 IEEE International Symposium on, pp. 115-115, 1998.
28. P. G. Gulak, "A Review of Multiple-Valued Memory Technology", The Twenty-Eighth International Symposium of Multiple-Valued Logic, Fukuoka, Japan, pp. 222-231, May 1998.
29. A. Sheikholeslami, R. Yoshimura, and P. G. Gulak, “Look-Up Tables (LUTs) for Multiple-Valued, Combinational Logic”, Proc. 28^th Int. Symposium on Multiple-Valued Logic, pp. 264-269, May 1998.
30. J. Omidi, S. Gazor, and P. G. Gulak, “Differential Kalman Filtering for Tracking Rayleigh Fading Channels”, 1998 IEEE Signal Processing Workshop on Signal Processing Systems (SiPS 98), pp. 376-392, April 1998.
31. V. Gaudet and P. G. Gulak, “CMOS Implementation of a Current Conveyor-Based Field-Programmable Analog Array”, 31st Alsilomar Conference, Signals, and Computers, Pacific Grove, CA, Nov. 2-5, 1997.
32. V. Gaudet and P. G. Gulak, “Towards a current conveyor based Field Programmable Analog arrays", ITRC annual retreat1997.
33. A. Sheikholeslami and P. G. Gulak, "Multivalued Ferroelectric Associative Memory Design", 6-th Workshop on Post-Binary ULSI Systems, Nova Scotia,     pp. 68-69, May 1997.
34. J. Omidi, P. G. Gulak, and S. Pasupathy, "Joint Data and Channel Estimation Using the Per-Branch Processing Method", Proceedings of the IEEE Signal             Processing Workshop on Wireless Communications, pp. 389-392, April 1997.
35. B.J. Frey, F.R. Kschischang, and P. G. Gulak, "Concurrent Turbo-Decoding", ISIT, Ulm, Germany, June 1997.
36. K. Schultz and P. G. Gulak, "Throttled-Buffer ATM Switch Output Control Circuitry with CAM-Based Multicast Support", ISSCC, San Francisco, pp. 152-153,  Feb 1997.
37. A. Sheikholeslami, P. G. Gulak, and T. Hanyu, "A Multiple-Valued Ferroelectric Content-Addressable Memory", Proceedings, 26^th International Symposium on, pp. 74-79, 1996.
38. P. G. Gulak, D. D'Mello, "A Review Field Programmable Analog Arrays", SPIE Conference, Boston, Oct 1996.
39. J. Omidi, P. G. Gulak and S. Pasupathy, "Parallel Structures for Joint Channel Estimation and Data Detection over Fading Channels", 1996 Workshop on VLSI Signal Processing, pp.325-336, Oct 1996.
40. B. Frey, F. Kschischang and P. G. Gulak, "Early Detection and Trellis Splicing: Reducing Complexity of Soft Iterative Decoding", Turbo Coding Workshop, Lund Institute of Technology, pp. 65-73, Aug 1996.
41. J. Omidi, S. Pasupathy and P. G. Gulak, "Joint Data and Kalman Estimation of Fading Channels Using a Generalized Viterbi Algorithm", 1996 IEEE International Communications Conference (ICC), Dallas, Vol. 2, pp. 1198-1203, June 1996.
42. P. G. Gulak, "Field-Programmable Analog Arrays: A Status Report" (Invited Paper), 4-th Canadian Workshop on Field Programmable Devices (FPD’96), Toronto, May 1996.
43. P. G. Gulak, "Field-Programmable Analog Arrays: Past, Present and Future Perspectives" (Invited Paper), TENCON 95, Hong Kong, Nov 1995.
44. P. Chow, P. Chow and P. G. Gulak, A Field-Programmable Mixed-Analog-Digital Array, FPGA'95.  

45. K. Schultz and P. G. Gulak, Physical Performance Limits for Shared Buffer ATM Switches to the Year 2005, International Switching Symposium (ISS), Berlin, April 1995.

46. E. Lee and P. G. Gulak, A Transconductor-Based Field Programmable Analog Array, ISSCC, San Francisco, Feb. 1995.

47. E. Lee and P. G. Gulak, MOS Transconductor-Based Field Programmable Analog Array, 3rd International Workshop on Post-Binary ULSI Systems, Boston,May 1994.

48. Q. Wang and P. G. Gulak, Design and Simulation of Data path-Oriented Reconfigurable Architectures , ASICON, Beijing, China, Oct. 1994.

49. G. Feygin, P. G. Gulak and P. Chow, Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression, Data Compression Conference DCC'94, Snowbird, Utah, March 1994, pp. 254-263.

50. K. Lowe and P. G. Gulak, A Unified Discrete Gate Sizing/Cell Library Optimization Method for Design and Analysis of Delay Minimized CMOS and BiCMOS Circuits, Euro-DAC'94, Grenoble, France, October 1994.

51. K. Lowe and P. G. Gulak, A Quick Way to Find the Optimized Performance of a Power Constrained BiCMOS Circuit, CICC'94, May 1994.

52. K. Schultz and P. G. Gulak, Fully Parallel Multi-Megabit Integrated CAM/RAM Design, IEEE International Workshop on Memory Technology, Design and Testing, Santa Clara, CA, August 1994.

53. K. Schultz and P. G. Gulak, The Telecom Machine: Memory-Intensive Reprogrammable Gigabit Switching, 17th Biennial Symposium on Communications, Kingston, May 1994, pp. 219-222.

54. K. Schultz and P. G. Gulak, Distributed Multicast Contention Resolution Using Content Addressable FIFOs, ICC '94, April 1994, pp. 1495-1500.

55. K. Schultz and P. G. Gulak, CAM-Based Single-Chip Shared Buffer ATM Switch, ICC '94, April 1994, pp. 1190-1195.

56. E. Lee and P. G. Gulak, A Transconductor-Based Field-Programmable Analog Array, 1994 ACM/SIGDA 2nd International Workshop on Field Programmable Gate Arrays, University of California, Berkeley, February 1994.

57. K. Schultz and P. G. Gulak, Architecture for Multi-Megabit Integrated CAM/RAM, CCVLSI, Banff, Alberta, November 1993, pp. 6A1-6A7. (Best Paper Award).

58. K. Lowe and P. G. Gulak, "Gate Sizing and Buffer Insertion for Optimizing Performance in Power Constrained BiCMOS Circuits", IEEE/ACM International Conference on CAD-93, Santa Clara, CA., November 7 - 10, 1993.

59. B. Herscovici and P. G. Gulak, "Reduced State Viterbi Receivers for Digital Mobile Communications", Milcom '93, Boston, October 9-12, 1993.

60. Q. Wang and P. G. Gulak, "An Array Architecture for Reconfigurable Datapaths", Oxford Conference on Field Programmable Systems, University of Oxford, England, September 7 - 10, 1994.

61. K. Schultz and P. G. Gulak, "A Logic-Enhanced Memory for Digital Data Recovery Circuits", ISCAS '93, Chicago, Vol. 3, pp. 2007-2010.

62. G. Feygin, P. Chow, P. G. Gulak, J. Chappel, G. Goodes, O. Hall, A. Sayes, S. Singh, M. Smith, S. Wilton, "A VLSI Implementation of a Cascade Viterbi Decoder with Traceback", ISCAS '93, Chicago, Vol. 3, pp. 1945-1948.

63. G. Feygin, P. G. Gulak and P. Chow, Minimizing Error and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding, IEEE Data Compression Conference, March 30-April 2, 1993, Snowbird, Utah, pp. 118-128.

64. E. Lee and P. G. Gulak, Dynamic Current-Mode Multi-Valued MOS Memory With Error Correction, International Symposium on Multiple-Valued Logic, Sendai, Japan, May 1992.

65. S. Wood, K.C. Smith and P. G. Gulak, Latched Differential FET Logic, 1991Int. Symposium on Circuits and Systems, Singapore, June 1991, pp. 3011-3014.

66. G. Feygin and P. G. Gulak, Survivor Sequence Memory Management in Viterbi Decoders, 1991 Int. Symposium on Circuits and Systems, Singapore, June 1991, pp. 2967-2970.

67. C.17 G. Feygin. P. G. Gulak and P. Chow, Generalized Cascade Viterbi Decoder - A Locally Connected Multiprocessor with Linear Speed-up, ICASSP, Toronto, May 1991, pp. 1097-1100.

68. E. Lee and P. G. Gulak, A CMOS Field-Programmable Analog Array, IEEE ISSCC'91, San Francisco, February 1991, pp. 186-188.

69. J. Erfanian, S. Pasupathy, P. G. Gulak, "Reduced Complexity Symbol Detectors with Parallel Structures", IEEE Global Telecommunications Conference, San Diego, December 1990, pp. 704-708.

70. S. Wood and P. G. Gulak, "High Speed DRAMs for ASIC Memory Applications", Canadian Conference on VLSI, Ottawa, October 1990, pp. 5.3.1-5.3.8.

71. E. Lee and P. G. Gulak, "Prototype Design of a Field-Programmable Analog Array", Canadian Conference on VLSI, Ottawa, October 1990, pp. 2.2.1-2.2.8.

72. J. Erfanian, J. Dao, P. G. Gulak and S. Pasupathy," Realization of the SPS Detection Algorithm on a Parallel VLSI Architecture", 15th Biennial Symposium on Communications, Kingston, Ontario, June 1990, pp. 41-44.

73. V.P. Roychowdhury, P. G. Gulak, A. Montalvao and T. Kailath, Decoding of Rate-k/n Convolutional Codes in VLSI, 1987 Princeton Workshop on Algorithm, Architecture and Technology Issues for Models of Concurrent Computation, Princeton, New Jersey, Sept. 30-Oct. 1, 1987, pp. 659-673.

74. P. G. Gulak, T. Kailath, A. Montalvo and V.P. Roychowdhury, Decoding Rate-k/n Convolutional Codes in VLSI, Fifth International Conference on Systems Engineering, Wright State University, Dayton, Ohio, Sept. 1987, pp. 83-86.

75. P. G. Gulak, V.P. Roychowdhury, T. Kailath, Decoding Convolutional Codes, in VLSI Third Joint USSR-Swedish International Conference on Information Theory, Sochi, USSR, May 1987.

76. M. Horowitz, J.L. Hennessy, P. C how, P. G. Gulak, J.M. Acken, A. Agarwal, C.Y. Chu, S.A. McFarling, S.A. Przybylski, S.E. Richardson, A. Salz, R.T. Simoni, D. Stark, P.A. Steenkiste, S. Tjiang and M.J. Wing, A 20 MIPS Peak Microprocessor with On-Chip Cache, ISSCC 87, Feb. 1987, pp. 30-32.

77. M. Horowitz, J.L. Hennessy, P. Chow, P. G. Gulak, J.M. Acken, A. Agarwal, C.Y. Chu, S.A. McFarling, S.A. Przybylski, S.E. Richardson, A. Salz, R.T. Simoni, D. Stark, P.A. Steenkiste, S. Tjiang and M.J. Wing, A 32b Microprocessor with on-chip 2Kbyte instruction cache, ISSCC 87, Feb. 1987, pp. 30-32.

78. K.D. Mann, P. G. Gulak and E. Shwedyk, A Shuffle Exchange Implementation of Viterbi's Algorithm using CMOS VLSI, 1985 Canadian Conference on Very Large Scale Integration, Toronto, Ontario, November 4-5, 1985, pp. 22-25.

79. M. Yunik, W. Pries, R.D. McLeod, G.E. Bridges, P. G. Gulak and H.C. Card, Dual Systolic Architectures for Digital Signal Processing in VLSI, 1984 Canadian Conference on Very Large Scale Integration, Edmonton Alberta, October 1-2, 1984, pp. 6.188-6.191.

80. P. G. Gulak, W. Pries, D. McLeod, H.C. Card, A Gate-Level CMOS Digital Logic Simulator in an Event-Driven Environment, 1984 Canadian Conference on Very Large Scale Integration, Edmonton, Alberta, October 1-2, 1984, pp. 3.90-3.93.

81. P. G. Gulak, VLSI Structures for Digital Communication Receivers, 1984 Canadian Conference on Very Large Scale Integration, Edmonton, Alberta, October 1-2, 1984, pp. 1.26-1.29.

82. P. G. Gulak and E. Shwedyk, Block Detection in a Normalized Kolmogorov Metric Space, Seventh International Conference on Pattern Recognition, Montreal, Canada, August 2, 1984, pp. 709-712.

83. K. Dickson, P. G. Gulak, D. Smith, PLA Generation Using a Silicon Assembler, 1983 Conference on Very Large Scale Integration, University of Waterloo, Waterloo, Ontario, Canada, October 24-25, 1983, pp. 22-25.

84. P. G. Gulak, E. Shwedyk, D. Card, Channel Capacity of a Computer Communication Channel, Tenth Biennial Symposium on Communications, Queen's University, Kingston, Ontario, Canada, May 28-30, 1980.