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  P. Glenn Gulak - Department of Electrical and Computer Engineering
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Publications Submitted to Refereed Journals for Review
    None in review.

 

Refereed Journal Publications
  1. N. Nikkhoo, P.G. Gulak, K. Maxwell, "Rapid detection of E.Coli bacteria using potassium-sensitive FETs in CMOS", IEEE Transactions on Biomedical Circuits and Systems, Submitted Mar. 2013.b

  2. M. Shabany, D. Patel, P.G. Gulak, "A Low-Latency Low-Power QR-Decomposition ASIC Implementation in 0.13um CMOS", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 60, No. 2, pp. 327-340, Feb. 2013. (NSERC)

  3. D. Ho, O. Noor, U. Krull, G. Gulak, and R. Genov, "CMOS Tunable-Wavelength Multi-Color Photogate Sensor", IEEE Trans. on Biomedical Circuits and Systems, accepted for publication. (NSERC).

  4. D. Ho, M. O. Noor, U. Krull, P.G. Gulak, R. Genov, "CMOS Tunable-Color Image Sensor With Dual-ADC Shot-Noise-Aware Dynamic Range Extension", IEEE Transactions on Circuits and Systems I: Regular Papers, DOI: 10.1109/TCSI.2013.2239115 (Early Access). (NSERC)

  5. D. Ho, M. O. Noor, U. Krull, P.G. Gulak, R. Genov, "CMOS Spectrally-Multiplexed FRET-on-a-Chip for DNA Analysis", IEEE Transactions on Biomedical Circuits and Systems, DOI: 10.1109/TBCAS.2012.2230172 (Early Access). (NSERC)

  6. V. Smolyakov, P. G. Gulak, T. Gallager, C. Ling, "Fault-Tolerant Embedded Memory Strategy for Baseband Signal Processing Systems", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, DOI: 10.1109/TVLSI.2012.2208208 (Early Access). (NSERC)

  7. M. Shabany, A. Youssef, P. G. Gulak, "High-Throughput 0.13um CMOS Lattice Reduction Core Supporting 880Mb/s Detection", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, DOI: 10.1109/TVLSI.2012.2198927 (Early Access). (NSERC)

  8. M. Zargham, P. G. Gulak, "Maximum Achievable Efficiency in Near-Field Coupled Power Transfer Systems", IEEE Transactions on Biomedical Circuits and Systems, Vol. 6, No. 3, pp. 228-245, Mar. 2012. (NSERC)

  9. M. Shabany, P. G. Gulak, "A 675 Mbps, 4x4 64-QAM K-Best MIMO Detector in 0.13um CMOS", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 1, pp. 135-147, Jan. 2012. (NSERC)

  10. R. Singh, D. Ho, A. Nilchi, P. G. Gulak P. Yau, R. Genov, "A CMOS/Thin-Film Fluorescence Contact Imaging Microsystem for DNA Analysis", IEEE Trans. on Circuits and Systems I: Regular Papers, Vol. 57, No. 5, pp. 1029-1038, May 2010. (NSERC)

  11. M. Shabany and P. G. Gulak, "Efficient Compensation of the Nonlinearity of Solid-State Power Amplifiers Using Adaptive Sequential Monte Carlo Methods", IEEE Transactions on Circuits and Systems I, Vol. 55, No. 10, pp. 3270-3283, 2008. (NSERC)

  12. W. J. Gross, F. R. Kschischang, and P. G. Gulak, "Architecture and Implementation of an Interpolation Processor for Soft-Decision Reed-Solomon Decoding", IEEE Transactions on VLSI Systems, Vol. 15, No. 3, pp. 309-318, March 2007. (NSERC)

  13. W. J. Gross, F. R. Kschischang, R. Koetter, and P. G. Gulak, "Applications of Algebraic Soft-Decision Decoding of Reed-Solomon Codes", IEEE Transactions on Communications, Vol. 54, No. 7, pp. 1224-1234, July 2006. (NSERC)

  14. Yadollah Eslami, Ali Sheikholeslami, Glenn Gulak, "An Area-Efficient Universal Cryptography Processor for Smart Cards", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 1, pp. 43-56, Jan. 2006. (NSERC, Fujitsu)

  15. D. Gnaedig, E. Boutillon, M. Jezequel, V. Gaudet and P. G. Gulak, "On Multiple Slice Turbo Codes", Annals of Telecommunications, Vol. 60,No.1-2, January/February 2005, pp.79-102.

  16. W. Gross, F. Kschischang, R. Koetter and P. G. Gulak, "Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Soloman Decoders", Journal of VLSI Signal Processing, Vol. 39, No. 1-2, 2005, pp. 93-111.

  17. V. Gaudet and P. G. Gulak, "A 13.3Mbps, 0.35um CMOS Analog Turbo Decoder IC with Configurable Interleaver" (invited), IEEE Journal of Solid-State Circuits, Nov. 2003.

  18. T. Esmailian, F.R. Kschischang, and P. G. Gulak, "In-Building Power Lines as High Speed Communication Channels: Channel Characterization and a Test Channel Ensemble", International Journal of Communication Systems, pp. 381-400, May 2003. (NSERC), Motorola.

  19. J. Siu, Y. Eslami, A. Sheikholeslami, P. G. Gu lak, T. Endo, and S. Kawashima, "A Current-Based Reference-Generation Scheme for 1T-1C Ferroelectric Random-Access Memories", IEEE Journal of Solid-State Circuits, Vol. 38, No. 3, March 2003, pp. 541-549.

  20. E. Boutillon, W. Gross, and P. G. Gulak, "VLSI Architectures for the MAP Algorithm", IEEE Trans. on Communications, Vol. 51, No. 2, Feb. 2003, pp. 175-185.

  21. V. Gaudet, R. Gaudet and P. G. Gulak, "Programmable Interleaver Design for Analog Iterative Decoders", IEEE Transactions on Circuits and Systems II - Analog and Digital Signal Processing, Vol. 49, No. 7, pp. 457-464, July 2002.

  22. W. Gross, V. Gaudet, and P. G. Gulak, "Difference Metric Soft-output Detection:  Architecture and Implementation", IEEE Transactions on Circuits and Systems II"Analog and Digital Signal Processing, Vol. 48, No. 10, pages 904-911, October 2001.

  23. Sheikholeslami, A., and P. G. Gulak, Takauchi, H., Tamura, H., Yoshioka, H., and Tamura, T.,  "A Pulse-Based, Parallel-Element Macromodel for Ferroelectric Capacitors", IEEE Trans. On Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 47, No. 4, July 2000, pp. 784-791.

  24. Sheikholeslami, A., and P. G. Gulak, "A Survey of Circuit Innovations in Ferroelectric Random-Access Memories", Proceedings of  the IEEE. Vol. 88, No. 5, May 2000, pp. 667-689.

  25. J. Omidi, P. G. Gulakand S. Pasupathy, "Parallel Structures for Joint Channel Estimation and Data Detection Over Fading Channels", IEEE Transactions on Selected Areas of Communications  (special issue on Signal Processing and Wireless Communications), Vol. 16, No. 9, pp. 1616-1629, Dec. 1998.

  26. Gaudet, V., and P. G. Gulak, "Implementation Issues for High-Bandwidth Field-Programmable Analog Arrays", Journal of Circuits, Systems, and Computers Special Issue on Analog and Digital Arrays, World Scientific Publishing, Vol. 8, No. 5-6, pages 541-558, 1998.

  27. W. Gross and P. G. Gulak, "Simplified MAP Algorithm suitable for implementation of turbo decoders", Electronics Letters, Aug. 6, 1998, Vol. 34, No. 16, pp. 1577-1578.

  28. D. R. D"Mello and P. G. Gulak, "Design Approaches to Field-Programmable Analog Integrated", (Special Issue on Programmable Analog Systems), Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, Vol. 17, No. 1-2, pp. 7-34, Sept. 1998.

  29. K. Lowe and P. G. Gulak, "A Joint Gate Sizing and Buffer Insertion Method for Optimizing Delay and Power in CMOS and BiCMOS Combinational Logic", IEEE Transactions on CAD, Vol. 17, No. 5, May 1998, pp. 419-434.

  30. K. Schultz and P. G. Gulak, "Physical Performance Limits for Shared Buffer ATM Switches", IEEE Transactions on Communications, Vol. 45, No. 8, pp. 997-1007, Aug. 1997.

  31. A. Sheikholeslami and P. G. Gulak, "A Survey of Behavioral Modeling of Ferroelectric Capacitors", IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, Vol. 44, No. 4, pp. 917-924, July 1997.

  32. K. Schultz and P. G. Gulak, "Multicast Contention Resolution with Single-Cycle Windowing Using Content Addressable FIFOs", IEEE/ACM Transactions on Networking, Vol. 4, No. 5, pp. 731-742, Oct. 1996.

  33. A. Sheikholeslami and P. G. Gulak, "Transient Modeling of Ferroelectric Capacitors for Semiconductor Memories", Microelectronic Engineering, Vol. 29, No. 1-4, 1995, pp. 141-144.

  34. A. Sheikholeslami and P. G. Gulak, "Transient Modeling of Ferroelectric Capacitors for Nonvolatile Memories", IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 43, No. 3, 1996, pp. 450-456.

  35. K. Schultz and P. G. Gulak, "Fully-Parallel Integrated CAM/RAM Using Pre-Classification to Enable Large Capacities", IEEE Journal of Solid-State Circuits, Vol. 31, No. 5, pp. 689-699, May 1996.

  36. K. Schultz and P. G. Gulak, "Architectures for Large-Capacity CAMs", Integration, the VLSI Journal, 18, No. 2-3, pp. 151-171, 1995.

  37. K. Schultz and P. G. Gulak, Throttled Buffer Asynchronous Switch for ATM, IEICE Transactions on Communications, (Special Issue on Future Private Networks),Vol. E77-B, No. 3, March 1994, pp. 351-358.

  38. G. Feygin, P. G. Gulak and P. Chow, Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding, The Journal of Information Processing and Management (Special Issue on Data Compression), Vol. 30, No. 6, pp. 805-816, Nov-Dec 1994.

  39. K. C. Smith and P. G. Gulak, Prospects for Multi-Valued Integrated Circuits (invited paper), IEICE Transactions on Electronics, Vol. E76-C, No. 3, March 1993, pp. 372-382.

  40. E. Lee and P. G. Gulak, Current-Mode Multivalued Dynamic MOS Memory with Error Correction, IEE Electronics Letters, Vol. 28, No. 11, May 1992, pp.1067-1069.

  41. E. Lee and P. G. Gulak, Field Programmable Analog Array Based on MOSFET Transconductors, IEE Electronics Letters, Vol. 28, No. 1, Jan. 1992, pp. 28-29.

  42. G. Feygin, P. G. Gulak and P. Chow, A Multiprocessor Architecture for Viterbi Decoders with Linear Speed-up, IEEE Transactions on Signal Processing, Vol. 41, No. 9, September 1993, pp. 2907 - 2917.

  43. J. Erfanian, S. Pasupathy, P. G. Gulak, Reduced Complexity Symbol Detectors with Parallel Structures for ISI Channels, IEEE Trans. on Communications, Vol. 42; No. 2/3/4, Feb/Mar/April, 1994, pp.1661-1671.

  44. G. Feygin and P. G. Gulak, Architectural Tradeoffs for Survivor Sequence Memory Management in Viterbi Decoders, IEEE Transactions on Communications, Vol. 41, No. 3, March 1993, pp. 425 - 429.

  45. E. Lee and P. G. Gulak, A CMOS Field Programmable Analog Array, IEEE J. of Solid State Circuits, Vol. 26, No. 12, December 1991, pp. 1860-1867.

  46. E. Lee and P. G. Gulak, Error Correction Technique for Multivalued MOS Memory, IEE Electronics Letters, Vol. 27, No. 15, July 18, 1991, pp. 1321-1323.

  47. P. G. Gulak and T. Kailath, Locally Connected VLSI Architectures for the Viterbi Algorithm, IEEE Journal on Selected Areas in Communications (Special Issue on VLSI in Communications), Vol. 6, No. 3, April 1988, pp. 527-537.

  48. M. Horowitz, P. Chow, M. Wing, D. Stark, R. Simoni, A. Salz, S. Przybylski, J. Hennessy, P. G. Gulak, A. Agarwal, J. Acken, MIPS-X: A 20 MIPS Peak, 32-Bit Microprocessor with On-Chip Cache, IEEE Journal of Solid State Circuits, Vol. SC-22, No. 5, October 1987, pp. 790-799.

  49. H.C. Card, P. G. Gulak, R.D. McLeod and W. Pries, (lT) Complexity Measures for VLSI Computations in Constant Chip Area, IEEE Transactions on Computers, Volume C-36, No. 1, January 1987, pp. 112-117.

  50. G.E. Bridges, W. Pries, R.D. McLeod, M. Yunik, P. G. Gulak and H.C. Card, Dual Systolic Architectures for VLSI Digital Signal Processing Systems, IEEE Transactions on Computers, Volume C-35, No. 10, October 1986, pp. 916-923.

  51. P. G. Gulak and E. Shwedyk, VLSI Structures for Viterbi Receivers: Part I - General Theory and Applications, IEEE Journal on Selected Areas in Communications (Special Issue on VLSI in Communications), Volume SAC-4, No. 1, January 1986, pp. 142-154.

  52. P. G. Gulak and E. Shwedyk, VLSI Structures for Viterbi Receivers:  Part II - Encoded MSK Modulation, IEEE Journal on Selected Areas in Communications (Special Issue on VLSI in Communications), Volume SAC-4, No. 1, January 1986, pp. 155-159.

  53. D.A. Buchanan and P. G. Gulak, Photocounting Statistics Associated with Temperature Fluctuations in Semiconductor Lasers, Journal of Applied Optics, Vol. 22, No. 1, January 1, 1983, pp. 37-48.

  54. P. G. Gulak, E. Shwedyk and D. Card, An Improved Approximation for the Isolated Transition in Saturated Magnetic Recording, IEEE Transactions on Magnetics,Vol.MAG-18, No. 5, 1982, pp. 989-992.

 

Refereed Conference Papers
  1. M. Zargham, P.G. Gulak, "A 0.13um CMOS Integrated Wireless Power Receiver for Biomedical Applications", IEEE European Solid State Circuits Conference (ESSCIRC), Submitted May 2013.

  2. N. Nikkhoo, P.G. Gulak, K. Maxwell, "Rapid Detection of E.Coli Bacteria using Potassium-sensitive FETs in CMOS", IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. 168-171, Nov. 2012. (NSERC) Best Paper Award

  3. D. Ho, M.O Noor, U. Krull, P.G. Gulak, R. Genov "Single-filter Multi-color CMOS Fluorescent Contact Sensing Microsystem", IEEE Int. Symp. on Circuits and Systems (ISCAS'12), pp. 2393-2396, 2012. (NSERC)

  4. D. Ho, P.G. Gulak, R. Genov "CMOS 3T Digital Pixel Sensor with In-pixel Shared Comparator", IEEE Int. Symp. on Circuits and Systems (ISCAS'12), pp. 930-933, 2012. (NSERC)

  5. M. Zargham, P.G. Gulak, "Fully-integrated Power-efficient Regulator and Bandgap Circuits for Wireless-powered Biomedical Applications", IEEE Int. Symp. on Circuits and Systems (ISCAS'12), pp. 2873-2876, 2012. (NSERC)

  6. M. Zargham, P.G. Gulak, "High-efficiency CMOS Rectifier for Fully Integrated mW Wireless Power Transfer", IEEE Int. Symp. on Circuits and Systems (ISCAS'12), pp. 2869-2872, 2012. (NSERC)

  7. S. Moradi, R. Doostnejad, P.G. Gulak, "Downlink Beamforming for FDD Systems with Precoding and Beam Steering", IEEE GlobeCOM, pp. 1-6, 2011. (NSERC)

  8. S. Moradi, P.G. Gulak, "A Robust RAM-THP Architecture for Downlink Multiuser MISO Transmission with User Scheduling", IEEE Signal Processing Systems (SIPS'11), pp. 334-339, 2011. (NSERC)

  9. D. Ho, P.G. Gulak, R. Genov "CMOS Field Modulated Color Sensor", IEEE Custom Integrated Circuits Conference (CICC), M-22, pp. 1-4, 2011. (NSERC)

  10. M. Zargham, P.G. Gulak, "Integrated CMOS Wireless Power Transfer for Neural Implants", IEEE Int. Symp. on Circuits and Systems (ISCAS'11), pp. 165-168, 2011. (NSERC)

  11. A. Youssef, M. Shabany, P.G. Gulak, "Performance Analysis of Lattice-Reduction Algorithms for a Novel LR-Compatible K-Best MIMO Detector", IEEE Int. Symp. on Circuits and Systems (ISCAS'11), pp. 701-704, 2011. (NSERC)

  12. D. Patel, V. Smolyakov, M. Shabany, P.G. Gulak, "A WiMAX/LTE Compliant Low-complexity 4x4 64-QAM Soft MIMO Receiver", IEEE 44th Asilomar Conf. on Signals, Systems and Computers (ASILOMAR), pp. 385-389, 2010. (NSERC)

  13. D. Patel, V. Smolyakov, M. Shabany, P.G. Gulak, "VLSI Implementation of a WiMAX/LTE Compliant Low-Complexity High-Throughput Soft-Output K-Best MIMO Detector", IEEE ISCAS 2010, June 2010. (NSERC)

  14. A. Youssef, M. Shabany, P.G. Gulak, "VLSI Implementation of a Hardware-Optimized Lattice-Reduction Algorithm for WiMAX/LTE MIMO Detection", IEEE Int. Symp. on Circuits and Systems, (ISCAS'10), pp. 3541-3544, 2010. (NSERC)

  15. R.R. Singh, D. Ho, A. Nilchi, R. Genov, P.G. Gulak, "A Hybrid Thin-film/CMOS Fluorescence Contact Imager", IEEE Int. Symp. on Circuits and Systems (ISCAS'09), pp. 2437-2440, 2009. (NSERC)

  16. D. Patel, M. Shabany, P.G. Gulak, "A Low-Complexity High-Speed QR Decomposition Implementation for MIMO Receivers", IEEE Int. Symp. on Circuits and Systems (ISCAS'09), pp. 33-36, 2009. (NSERC)

  17. M. Shabany, P.G. Gulak, "A 0.13um CMOS 655Mb/s 64-QAM K-Best 4x4 MIMO Detector", 2009 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC'09), pp. 256-257, Feb. 2009. (NSERC)

  18. N. Nikkhoo, C. Mann, P.G. Gulak and K. Maxwell, "A CMOS Integrated Bacterial Sensor for Rapid Detection of Pseudomonas aeruginosa", IEEE Biomedical Circuits and Systems Conference, (BioCAS), pp. 213-216, Nov. 2008. (NSERC, CIHR)

  19. M. Shabany, P.G. Gulak, "A Systolic Architecture of a Sequential Monte Carlo-based Equalizer for Frequency-Selective MIMO Channels", IEEE Workshop on Signal Processing Systems (SIPS'08), pp. 67-72, Oct. 2008. (NSERC)

  20. M. Shabany, P.G. Gulak, "A Scalable VLSI Architecture for K-Best Lattice Decoders", IEEE International Symposium on Circuits and Systems (ISCAS'08), pp. 940-943, May 2008. (NSERC)

  21. M. Shabany, P.G. Gulak, "The Application of Lattice-Reduction to the K-Best Algorithm for Near-Optimal MIMO Detection", IEEE Int. Symp. on Circuits and Systems (ISCAS'08), pp. 316-319, May 2008. (NSERC)

  22. M. Shabany, K. Su, P.G. Gulak, "A Pipelined Scalable High-Throughput Implementation of a Near-ML Complex K-Best Complex Lattice Decoders", IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP'08), pp. 3173-3176, April 2008. (NSERC)

  23. N. Nikkhoo, C. Mann, K. Maxwell, P.G. Gulak, "A 0.18um CMOS Integrated Sensor for the Rapid Identification of Bacteria", 2008 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC'08), pp. 336-337, Feb. 2008. (NSERC)

  24. M. Shabany, P.G. Gulak, "Application of Sequential Monte Carlo to M-QAM Schemes in the Presence of Nonlinear Solid-State Power Amplifiers", IEEE Int. Symp. on Circuits and Systems (ISCAS'07), pp. 2295-2298, 2007, Best Student Paper Award Nominee. (NSERC)

  25. S. Parikh, P.G. Gulak, P. Chow, "A CMOS Image Sensor for DNA Microarrays", Custom Integrated Circuits Conference (CICC), pp. 821-824, Sept. 2007. (NSERC)

  26. K. Kasiri, I. Hosseini, O. Taheri, M.J. Omidi, P.G. Gulak, "A Preprocessing Method for PAPR Reduction in OFDM Systems by Modifying FFT and IFFT Matrices", IEEE Int. Symp. on Personal, Indoor and Mobile Radio Communications (PIMRC'07), pp. 1-5, 2007.

  27. M. Shabany, P. G. Gulak, "VLSI Implementation of a Sequential Monte Carlo Receiver", IEEE International Symposium on Circuits and Systems (ISCAS'06), Greece, May 21-24, 2006.

  28. M. Shabany, P. G. Gulak, "An Efficient Architecture for Distributed Resampling for High-Speed Particle Filtering", IEEE International Symposium on Circuits and Systems (ISCAS'06), Greece, May 21-24, 2006.

  29. I. Hosseini, M. J. Omidi, K. Kasiri, A. Sadri, P. G. Gulak, "PAPR Reduction in OFDM Systems Using Polynomial-based Compressing and Iterative Expanding", ICASSP 2006, Toulouse, France, May 14-19, 2006.

  30. M. Shabany, H. Shojania, J. Zhang, J. Omidi, P. G. Gulak, "VLSI Architecture of a Wireless Channel Estimator Using Sequential Monte Carlo Methods", IEEE Workshop on Signal Processing Advances in Wireless Communications (SPAWC'05), 2005.

  31. H. Zamiri-Jafarian and P.G.Gulak, "Adaptive Channel SVD Estimation for MIMO-OFDM Systems" (Session 5B), IEEE 61st Semiannual Vehicular Technology Conference, Stockholm, Sweden, May 30-June 1, 2005.

  32. H. Zamiri-Jafarian and P.G.Gulak, "Iterative MIMO Channel SVD Estimation", IEEE International Conference on Communications, Seoul, Korea, May 16-20, 2005.

  33. W. Gross, F. Kschischang and P. G. Gulak, "An FPGA Interpolation Engine for Soft-Decision Reed-Soloman Decoding", Proceedings of the 2004 Symposium on Field-Programmable Custom Computing Machines, April 2004.

  34. D. Gnaedig, E. Boutillon, M. Jezequel, V. Gaudet, and P. G. Gulak, "On Multiple Slice Turbo Codes", 3rd Int. Symposium on Turbo Codes and Related Topics, Brest, France, Sept. 2003, pp. 343-346.

  35. V. Gaudet and P. G. Gulak, "A 13.3Mbps, 0.35um CMOS Analog Turbo Decoder IC with a Configurable Interleaver", 2003 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 148-149, 484, Feb. 2003.

  36. W. Gross, F. Kschischang, R. Koetter, and P. G. Gulak, "A VLSI Architecture for Interpolation in Soft-Decision List Decoding of Reed-Solomon Codes", Proc. of the 2002 IEEE Workshop on Signal Processing Systems, SIPS'02, San Diego, Oct. 2002, pp. 39-44.

  37. T. Fill and P. G. Gulak, "An Assessment of VLSI and Embedded Software Implementations for Reed Solomon Decoders, IEEE Signal Processing Systems SIPS"02, Oct. 2002, pp. 99-102.

  38. K. Pagiamtzis and P. G. Gulak, "Empirical Performance Prediction for IFFT/FFT cores for OFDM Systems-on-a-Chip, IEEE Midwest Symposium on Circuits and Systems, August 2002, Vol. 1, pp. 583-586.

  39. W. Gross, F. Kschischang, R. Koetter, and P. G. Gulak, "Simulation Results for Algebraic Soft-Decision Decoding of Reed-Solomon Codes", Proc. of the 21st Biennial Symposium on Communications, June 2002, Queen's University, Kingston, Canada, pp. 356-360.

  40. J. Siu, Y. Eslami, A. Sheikholeslami, P. G. Gulak, T. Endo, and S. Kawashima, "A 16kb 1T1C FeRAM Testchip Using Current-Based Reference Scheme", IEEE Custom Integrated Circuit Conference, pp. 107-110, May 2002.

  41. T. Esmailian, F.R. Kschischang, and P. G. Gulak. "A 32-Point Multiplier-Free Approximate FFT," Proceedings of the 21st Biennial Symposium on Communications, Queen's University, June 2002, pp. 448-452.

  42. T. Esmailian, F. R. Kschischang, and P. G. Gulak, "An In-Building Power Line Channel Simulator", Proceedings of the 2002 International Symposium on Power Line Communications and its Applications, ISPLC2002, pp. 31-35, March 2002, Athens, Greece.

  43. T. Esmailian, F.R. Kschischang, and P. G. Gulak, "Capacity Distribution of Radiation-Limited In-Building Power Lines", Proceedings of the 2002 International Symposium on Power Line Communications and its Applications, ISPLC2002, pp. 118-122, March 2002, Athens, Greece.

  44. Y. Eslami, J. Siu, A. Sheikholeslami, P. G. Gulak, T. Endo, and S. Kawashima, "A 2T-2C FeRAM Testchip for Optimum Bitline and Cell  Capacitances", Proc. Of the 1st Int'l Meeting on Ferroelectric Random Access Memories, pp. 178-179, Nov. 2001.

  45. A. Ghazel, E. Boutillon, J.-L. Danger, P. G. Gulak, H. Laamari, "Design and Performance Analysis of a High-Speed AWGN Communications Channel Emulator", 2001 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Aug. 2001, Volume 2, pp. 374-377.

  46. N. Sohi and P. G. Gulak, "A Multi-Standard Set-Top Box Channel Decoder", IEEE Signal Processing Systems, SIPS"00, Oct. 2000, pp. 295-304.

  47. W. Gross, V. Gaudet and P. G. Gulak, "A VLSI Architecture for Soft-output PR4 Detection", 2000 IEEE Midwest Symposium on Circuits and Systems, August 2000, Vol. 1, pp. 416-419.

  48. Boutillon, E., Gross, W., and Gulak, G., "Gestion De La Memoire Pour L'Algorithme Du Forward Backward", 5eme Workshop AAA sur 'Adequation Algorithme Architecture, 26-28 Jan. 2000, INRIA Rocquencourt, France.

  49. Esmailian, T., Gulak, G., and Kschischang, F., "A Discrete Multitone Power Line Communications System", IEEE Int. Conference on Acoustics, Speech, and Signal Processing, ICASSP 2000, Istanbul, Turkey, Vol. 5, pp. 2953-2956.

  50. Esmailian, T., Kschischang, F., and Gulak, G., "Simulation of a Discrete Multitone System Over In-Building Power Line", 20th Biennial Symposium on Communications, Queen"s University, May 2000, pp. 32-36.

  51. Esmailian, T., Kschischang, F., and Gulak, G., "Characteristics of In-Building Power Lines at High Frequencies and their Channel Capacity", Proceedings of 2000 Int. Symposium on Power-Line Communications and its Applications, pp. 52-59, ISPLC 2000, Limerick, Ireland.

  52. J. Podaima and P. G. Gulak, "Self-Timed Fully Parallel Content Addressable Queue for Switching Applications, CICC, pp. 239-242, May 1999, paper 11.4.

  53. A.H. Banihasherni, Frank, R. Kschischang, P. G. Gulak, "On Tanner Graphs of Lattices and Codes", Information Theory, Proceedings, 1998 IEEE International Symposium on, pp. 115-115, 1998.

  54. P. G. Gulak, "A Review of Multiple-Valued Memory Technology", The Twenty-Eighth International Symposium of Multiple-Valued Logic, Fukuoka, Japan, pp. 222-231, May 1998.

  55. A. Sheikholeslami, R. Yoshimura, and P. G. Gulak, "Look-Up Tables (LUTs) for Multiple-Valued, Combinational Logic", Proc. 28th Int. Symposium on Multiple-Valued Logic, pp. 264-269, May 1998.

  56. J. Omidi, S. Gazor, and P. G. Gulak, "Differential Kalman Filtering for Tracking Rayleigh Fading Channels", 1998 IEEE Signal Processing Workshop on Signal Processing Systems (SiPS 98), pp. 376-392, April 1998.

  57. V. Gaudet and P. G. Gulak, "CMOS Implementation of a Current Conveyor-Based Field-Programmable Analog Array", 31st Alsilomar Conference, Signals, and Computers, Pacific Grove, CA, Nov. 2-5, 1997.

  58. V. Gaudet and P. G. Gulak, "Towards a current conveyor based Field Programmable Analog arrays", ITRC annual retreat1997.

  59. A. Sheikholeslami and P. G. Gulak, "Multivalued Ferroelectric Associative Memory Design", 6-th Workshop on Post-Binary ULSI Systems, Nova Scotia,     pp. 68-69, May 1997.

  60. J. Omidi, P. G. Gulak, and S. Pasupathy, "Joint Data and Channel Estimation Using the Per-Branch Processing Method", Proceedings of the IEEE Signal Processing Workshop on Wireless Communications, pp. 389-392, April 1997.

  61. B.J. Frey, F.R. Kschischang, and P. G. Gulak, "Concurrent Turbo-Decoding", ISIT, Ulm, Germany, June 1997.

  62. K. Schultz and P. G. Gulak, "Throttled-Buffer ATM Switch Output Control Circuitry with CAM-Based Multicast Support", ISSCC, San Francisco, pp. 152-153,  Feb 1997.

  63. A. Sheikholeslami, P. G. Gulak, and T. Hanyu, "A Multiple-Valued Ferroelectric Content-Addressable Memory", Proceedings, 26th International Symposium on, pp. 74-79, 1996.

  64. P. G. Gulak, D. D'Mello, "A Review Field Programmable Analog Arrays", SPIE Conference, Boston, Oct 1996.

  65. J. Omidi, P. G. Gulak and S. Pasupathy, "Parallel Structures for Joint Channel Estimation and Data Detection over Fading Channels", 1996 Workshop on VLSI Signal Processing, pp.325-336, Oct 1996.

  66. B. Frey, F. Kschischang and P. G. Gulak, "Early Detection and Trellis Splicing: Reducing Complexity of Soft Iterative Decoding", Turbo Coding Workshop, Lund Institute of Technology, pp. 65-73, Aug 1996.

  67. J. Omidi, S. Pasupathy and P. G. Gulak, "Joint Data and Kalman Estimation of Fading Channels Using a Generalized Viterbi Algorithm", 1996 IEEE International Communications Conference (ICC), Dallas, Vol. 2, pp. 1198-1203, June 1996.

  68. P. G. Gulak, "Field-Programmable Analog Arrays: A Status Report" (Invited Paper), 4-th Canadian Workshop on Field Programmable Devices (FPD"96), Toronto, May 1996.

  69. P. G. Gulak, "Field-Programmable Analog Arrays: Past, Present and Future Perspectives" (Invited Paper), TENCON 95, Hong Kong, Nov 1995.

  70. P. Chow, P. Chow and P. G. Gulak, "A Field-Programmable Mixed-Analog-Digital Array", FPGA'95.

  71. K. Schultz and P. G. Gulak, "Physical Performance Limits for Shared Buffer ATM Switches to the Year 2005", International Switching Symposium (ISS), Berlin, April 1995.

  72. E. Lee and P. G. Gulak, "A Transconductor-Based Field Programmable Analog Array", ISSCC, San Francisco, Feb. 1995.

  73. E. Lee and P. G. Gulak, "MOS Transconductor-Based Field Programmable Analog Array", 3rd International Workshop on Post-Binary ULSI Systems, Boston,May 1994.

  74. Q. Wang and P. G. Gulak, "Design and Simulation of Data path-Oriented Reconfigurable Architectures", ASICON, Beijing, China, Oct. 1994.

  75. G. Feygin, P. G. Gulak and P. Chow, "Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression", Data Compression Conference DCC'94, Snowbird, Utah, March 1994, pp. 254-263.

  76. K. Lowe and P. G. Gulak, A Unified Discrete Gate Sizing/Cell Library Optimization Method for Design and Analysis of Delay Minimized CMOS and BiCMOS Circuits, Euro-DAC'94, Grenoble, France, October 1994.

  77. K. Lowe and P. G. Gulak, A Quick Way to Find the Optimized Performance of a Power Constrained BiCMOS Circuit, CICC'94, May 1994.

  78. K. Schultz and P. G. Gulak, Fully Parallel Multi-Megabit Integrated CAM/RAM Design,IEEE International Workshop on Memory Technology, Design and Testing, Santa Clara, CA, August 1994.

  79. K. Schultz and P. G. Gulak, The Telecom Machine: Memory-Intensive Reprogrammable Gigabit Switching, 17th Biennial Symposium on Communications, Kingston, May 1994, pp. 219-222.

  80. K. Schultz and P. G. Gulak, Distributed Multicast Contention Resolution Using Content Addressable FIFOsICC '94, April 1994, pp. 1495-1500.

  81. K. Schultz and P. G. Gulak, CAM-Based Single-Chip Shared Buffer ATM Switch,ICC '94, April 1994, pp. 1190-1195.

  82. E. Lee and P. G. Gulak, A Transconductor-Based Field-Programmable Analog Array, 1994 ACM/SIGDA 2nd International Workshop on Field Programmable Gate Arrays, University of California, Berkeley, February 1994.

  83. K. Schultz and P. G. Gulak, Architecture for Multi-Megabit Integrated CAM/RAM, CCVLSI, Banff, Alberta, November 1993, pp. 6A1-6A7. (Best Paper Award).

  84. K. Lowe and P. G. Gulak, "Gate Sizing and Buffer Insertion for Optimizing Performance in Power Constrained BiCMOS Circuits",IEEE/ACM International Conference on CAD-93, Santa Clara, CA., November 7 - 10, 1993.

  85. B. Herscovici and P. G. Gulak, "Reduced State Viterbi Receivers for Digital Mobile Communications", Milcom '93, Boston, October 9-12, 1993.

  86. Q. Wang and P. G. Gulak, "An Array Architecture for Reconfigurable Datapaths", Oxford Conference on Field Programmable Systems, University of Oxford, England, September 7 - 10, 1994.

  87. K. Schultz and P. G. Gulak, "A Logic-Enhanced Memory for Digital Data Recovery Circuits", ISCAS '93, Chicago, Vol. 3, pp. 2007-2010.

  88. G. Feygin, P. Chow, P. G. Gulak, J. Chappel, G. Goodes, O. Hall, A. Sayes, S. Singh, M. Smith, S. Wilton, "A VLSI Implementation of a Cascade Viterbi Decoder with Traceback", ISCAS '93, Chicago, Vol. 3, pp. 1945-1948.

  89. G. Feygin, P. G. Gulak and P. Chow, Minimizing Error and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding, IEEE Data Compression Conference, March 30-April 2, 1993, Snowbird, Utah, pp. 118-128.

  90. E. Lee and P. G. Gulak, Dynamic Current-Mode Multi-Valued MOS Memory With Error Correction, International Symposium on Multiple-Valued Logic, Sendai, Japan, May 1992.

  91. S. Wood, K.C. Smith and P. G. Gulak, Latched Differential FET Logic, 1991Int. Symposium on Circuits and Systems, Singapore, June 1991, pp. 3011-3014.

  92. G. Feygin and P. G. Gulak, Survivor Sequence Memory Management in Viterbi Decoders, 1991 Int. Symposium on Circuits and Systems, Singapore, June 1991, pp. 2967-2970.

  93. G. Feygin, P. G. Gulak and P. Chow, Generalized Cascade Viterbi Decoder - A Locally Connected Multiprocessor with Linear Speed-up, ICASSP, Toronto, May 1991, pp. 1097-1100.

  94. E. Lee and P. G. Gulak, A CMOS Field-Programmable Analog Array,IEEE ISSCC'91, San Francisco, February 1991, pp. 186-188.

  95. J. Erfanian, S. Pasupathy, P. G. Gulak, "Reduced Complexity Symbol Detectors with Parallel Structures", IEEE Global Telecommunications Conference, San Diego, December 1990, pp. 704-708.

  96. S. Wood and P. G. Gulak, "High Speed DRAMs for ASIC Memory Applications", Canadian Conference on VLSI, Ottawa, October 1990, pp. 5.3.1-5.3.8.

  97. E. Lee and P. G. Gulak, "Prototype Design of a Field-Programmable Analog Array", Canadian Conference on VLSI, Ottawa, October 1990, pp. 2.2.1-2.2.8.

  98. J. Erfanian, J. Dao, P. G. Gulak and S. Pasupathy," Realization of the SPS Detection Algorithm on a Parallel VLSI Architecture", 15th Biennial Symposium on Communications, Kingston, Ontario, June 1990, pp. 41-44.

  99. V.P. Roychowdhury, P. G. Gulak, A. Montalvao and T. Kailath, Decoding of Rate-k/n Convolutional Codes in VLSI, 1987 Princeton Workshop on Algorithm, Architecture and Technology Issues for Models of Concurrent Computation, Princeton, New Jersey, Sept. 30-Oct. 1, 1987, pp. 659-673.

  100. P. G. Gulak, T. Kailath, A. Montalvo and V.P. Roychowdhury, Decoding Rate-k/n Convolutional Codes in VLSI, Fifth International Conference on Systems Engineering, Wright State University, Dayton, Ohio, Sept. 1987, pp. 83-86.

  101. P. G. Gulak, V.P. Roychowdhury, T. Kailath, Decoding Convolutional Codes, in VLSI Third Joint USSR-Swedish International Conference on Information Theory, Sochi, USSR, May 1987.

  102. M. Horowitz, J.L. Hennessy, P. Chow, P. G. Gulak, J.M. Acken, A. Agarwal, C.Y. Chu, S.A. McFarling, S.A. Przybylski, S.E. Richardson, A. Salz, R.T. Simoni, D. Stark, P.A. Steenkiste, S. Tjiang and M.J. Wing, A 32b Microprocessor with on-chip 2Kbyte instruction cache, ISSCC 87, Feb. 1987, pp. 30-32.

  103. K.D. Mann, P. G. Gulak and E. Shwedyk, A Shuffle Exchange Implementation of Viterbi's Algorithm using CMOS VLSI, 1985 Canadian Conference on Very Large Scale Integration, Toronto, Ontario, November 4-5, 1985, pp. 22-25.

  104. M. Yunik, W. Pries, R.D. McLeod, G.E. Bridges, P. G. Gulak and H.C. Card, Dual Systolic Architectures for Digital Signal Processing in VLSI, 1984 Canadian Conference on Very Large Scale Integration, Edmonton Alberta, October 1-2, 1984, pp. 6.188-6.191.

  105. P. G. Gulak, W. Pries, D. McLeod, H.C. Card, A Gate-Level CMOS Digital Logic Simulator in an Event-Driven Environment, 1984 Canadian Conference on Very Large Scale Integration, Edmonton, Alberta, October 1-2, 1984, pp. 3.90-3.93.

  106. P. G. Gulak, VLSI Structures for Digital Communication Receivers, 1984 Canadian Conference on Very Large Scale Integration, Edmonton, Alberta, October 1-2, 1984, pp. 1.26-1.29.

  107. P. G. Gulak and E. Shwedyk, Block Detection in a Normalized Kolmogorov Metric Space, Seventh International Conference on Pattern Recognition, Montreal, Canada, August 2, 1984, pp. 709-712.

  108. K. Dickson, P. G. Gulak, D. Smith, PLA Generation Using a Silicon Assembler, 1983 Conference on Very Large Scale Integration, University of Waterloo, Waterloo, Ontario, Canada, October 24-25, 1983, pp. 22-25.

  109. P. G. Gulak, E. Shwedyk, D. Card, Channel Capacity of a Computer Communication Channel, Tenth Biennial Symposium on Communications, Queen's University, Kingston, Ontario, Canada, May 28-30, 1980.

 

Patents
  1. D. Patel, M. Shabany, P.G. Gulak, "Signal Processing Block for a Receiver in Wireless Communication", USPTO No. 12/786,288, filed on May 24, 2010, licensed to MaxLinear Inc.

  2. D. Patel, M. Shabany, P.G. Gulak, "Method and System for a Low-complexity Soft-output MIMO Detection", USPTO No. 13/149,743, filed on May 31, 2011, licensed to MaxLinear Inc.

  3. C. Ling, V. Smolyakov, T. Gallagher, P.G. Gulak, "Method and Apparatus for Memory Fault Tolerance", USPTO No. 13/269,416, filed on Oct. 7, 2011, Assignee MaxLinear Inc.

  4. A. Sheikholeslami, P. G. Gulak, and T. Hanyu, "Multiple-Valued Ferroelectric Content-Addressable Memory", U.S. Patent # 5,808,929, Sept. 15, 1998.

  5. A. Sheikholesalmi, P. G. Gulak, and T. Hanyu, "Nonvolatile Content Addressable Memory", U.S. Patent #5,930,161, July 27, 1999.

  6. E. Boutillon, P. G. Gulak, V. Gaudet and D. Gnaedig, "Procede de codage et/ou de decodage de codes correcteurs d'erreurs, dispositifs et systeme correspondants", French patent #2838581, granted October 17, 2003

 

Symposia/Colloquia/Unrefereed Conferences
  1. P. G. Gulak, A VLSI Viterbi Decoder for Galileo (Invited presentation), Algorithms and Parallel VLSI Architectures II, Bonas, France, June 3-6, 1991.

  2. E. Lee and P. G. Gulak, A CMOS Field-Programmable Analog Array for Signal Processing Applications, IEEE VLSI Workshop, Tampa, Florida, Feb. 17, 1990.

  3. P. G. Gulak, An Undergraduate Course in VLSI Systems, VLSI in Education Conference, Santa Clara, July 1989.

  4. G. Feygin, P. G. Gulak and F. Pollara, Survivor Sequence Memory Management in Viterbi Decoders, Proceedings of the Third Workshop on ECC, IBM Almaden Research Center, September 18 and 19, 1989.

  5. P. G. Gulak, VLSI Architectures for Digital Communications (Invited presentation), NATO ASI Workshop on Customized VLSI Architectures for Real-Time Signal and Numerical Processing, Belgium, July 28-29, 1988.

  6. T. Kailath, P. G. Gulak, V.P. Roychowdhury and A. Montalvo, Decoding Convolutional Codes in VLSI, 21st Annual Asilomar Conference, Monterey, CA, Oct. 1987.

  7. P. G. Gulak, V.P. Roychowdhury and T. Kailath, Decoding Convolutional Codes in VLSI, 1986 International Symposium on Information Theory, Ann Arbor, Michigan, October 1986.

  8. P. G. Gulak and T. Kailath, Locally Connected VLSI Architectures for the Viterbi Algorithm, 2nd Annual IBM Workshop in Coding Theory, IBM Almaden Research Center, San Jose, CA, Sept. 1987.

  9. P. G. Gulak, V.P. Roychowdhury, A. Montalvo, and T. Kailath, Decoding of Rate-k/n Convolutional Codes in VLSI, International Workshop on Information Theory, Como, Italy, July 2-5, 1987.

  10. P. G. Gulak, Considerations for Concurrent Decoding of Rate-k/n Convolutional Codes, 1st Annual IBM Workshop in Coding Theory, IBM Almaden Research Center, San Jose, CA, August 1986.

 

Technical Reports
  1. G. Feygin and P. G. Gulak, Survivor Sequence Memory Management in Viterbi Decoders, Technical Report CSRI-252, Computer Systems Research Institute, University of Toronto, Jan. 1991, 24 pages.

  2. P. G. Gulak, An Undergraduate Course on VLSI Systems - Progress Report, Dept. of Electrical Engineering, University of Toronto, submitted to the Canadian Microelectronics Corporation, June 1990.

  3. P. G. Gulak, Studies on Convolutional Codes: Theory and Implementation, Technical Report Submitted to Rockwell International, Information Systems Laboratory, Stanford University, Dec. 1986, 86 pages.

  4. P. G. Gulak, Signal Name Conventions for MIPS-X, MIPS-X Working Paper #41, Computer Systems Laboratory, Stanford University, Sept. 1985.

  5. D. Burek and P. G. Gulak, A Three-Dimensional Contour Measurement System using Moire Techniques, A Technical Report Submitted to Diffracto Limited, Windsor, Ontario, 1983, 82 pages.

  6. D. Burek and P. G. Gulak, Design of an Image Processing Workstation, A Technical Report Submitted to Diffracto Limited, Windsor, Ontario, 1982, 112 pages.

  7. P. G. Gulak, The Longitudinal Magnetic Recorder as a Digital Communications Channel, A Technical Report Submitted to the Burroughs Corporation, Winnipeg, Manitoba, February 1980, 96 pages.