ECE452 - Computer Architecture

Fall 2009
Department of Electrical and Computer Engineering
University of Toronto

Instructors:
Prof. Paul Chow
Prof. Natalie Enright Jerger
MAIN | COURSE OUTLINE | ASSIGNMENTS | MIDTERM & FINAL
Instructors:

Prof. Paul Chow

EA320 (Engineering Annex), Tel: 978-2402, Email: pc at eecg dot toronto dot edu

Prof. Natalie Enright Jerger

PT374A (Pratt Buidling), Tel: 978-5056, Email: enright at eecg dot toronto dot edu

IMPORTANT!

If you miss the midterm due to illness, please register your condition on ROSI according to the University policy: http://www.preparedness.utoronto.ca/ and send a copy of the confirmation to Prof. Chow (pc@eecg.toronto.edu). The 30% for the midterm will be allocated to the final, making the final 75%.

Course Description. This course provides students with a solid understanding of fundamental architectural techniques used to build today's high-performance processors and systems. Course topics include pipelining, caches, virtual memory, and multiprocessors. Some emphasis will be placed on hardware/software interaction to achieve performance.

Course Timetable

LEC01: Prof. Paul Chow
  • Mon 1-2pm BA 1220
  • Wed 1-2pm GB 220
  • Fri 12-1pm BA 1210
LEC02: Prof. Natalie Enright Jerger
  • Mon 10-11 GB 120
  • Wed 10-11 GB 244
  • Fri 10-11 BA 1200
Tutorials
  • Friday TUT01 11am - 12noon RS208
  • Friday TUT02 4pm - 5pm GB412

Evaluation Scheme

   Assignments 25%
   Midterm 30%
   Final 45%
Required Textbook:
J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach, 4th edition.

External Web Resources

Local Web Resources

MAIN | COURSE OUTLINE | ASSIGNMENTS | MIDTERM & FINAL