
ECE-1387: CAD for Digital Circuit Synthesis and
Layout
Spring 2010
NEWS:
-
Assignment #1
(routing) is now due on February 17 at 11:59 PM by email to the
instructor. Late submissions will be penalized as noted on the
handout. (Feb 7)
-
Notes for lecture #2 are posted. (Feb 9)
Basic Information
Instructor:
Jason Anderson
E-mail:
janders@eecg.toronto.edu
Web: http://www.eecg.toronto.edu/~janders
Tel:
416-946-7285
Office:
EA314 (Engineering Annex)
Instructor's Office hours:
Email or phone for an appointment (or drop by my office)
Lectures: Wednesdays from
noon-2PM in BA 4164 (Bahen Building)
Overview
The course
covers the approaches and algorithms for automatic circuit synthesis,
with a
concentration on the back-end of the CAD flow. Topics covered
will
include: technology mapping, partitioning, placement, routing, timing
analysis, and physical synthesis. The course will include
experience
with existing CAD tools and building new tools in C. We will pay
special
attention to synthesis issues as applied to Field-Programmable Gate
Arrays (FPGAs).
This
course will interest students whose research falls in the area of CAD
and/or VLSI/FPGA architectures. The course should also be of
value to
digital circuit designers, and anyone interested in learning about
practical applications of combinatorial optimization algorithms.
Scribe Schedule and Lecture Notes
| Lecture Number/Date |
Scribe Name and Notes (PPT, PDF) |
| #2 Jan 27 |
Kit (PPT, PDF) PPT is recommended as there is an animation. |
| #3 Feb 3 |
|
| #4 Feb 10 |
|
| #5 Feb 24 |
|
| #6 Mar 3 |
|
| #7 Mar 10 |
|
| #8 Mar 17 |
|
| #9 Mar 24 |
|
| #10 Mar 31 |
|
| #11 Apr 7 |
|
| #12 Apr 14 |
N/A -- guest lecture |
Assignments
Graphics
package documentation (PDF)
Graphics
package source code
Assignment #1 -- Routing (PDF) -- Assigned:
Jan 27, 2010; Due: Feb 17, 2010. Note:
Assignment #1 is now due on Feb 17 at 11:59 PM by email to the
instructor.
Exercises
|