ECE-1387: CAD for Digital Circuit Synthesis and Layout
Spring 2009
Instructor Info
Instructor: Jason Anderson
Email: janders@eecg.toronto.edu
Web: http://www.eecg.toronto.edu/~janders
Tel: 416-946-7285
Office: EA314 (Engineering Annex)
Office hours: Email or phone for an appointment
Email: janders@eecg.toronto.edu
Web: http://www.eecg.toronto.edu/~janders
Tel: 416-946-7285
Office: EA314 (Engineering Annex)
Office hours: Email or phone for an appointment
Overview
The course covers the approaches and algorithms for automatic circuit synthesis, with a
concentration on the back-end of the CAD flow. Topics covered will
include: technology mapping, partitioning, placement, routing, timing
analysis, and physical synthesis. The course will include experience
with existing CAD tools and building new tools in C. We will pay special
attention to synthesis issues as applied to Field-Programmable Gate
Arrays (FPGAs).
This course will interest students whose research falls in the area of CAD and/or VLSI/FPGA architectures. The course should also be of value to digital circuit designers, and anyone interested in learning about practical applications of combinatorial optimization algorithms.
This course will interest students whose research falls in the area of CAD and/or VLSI/FPGA architectures. The course should also be of value to digital circuit designers, and anyone interested in learning about practical applications of combinatorial optimization algorithms.
Lectures
Time: Fridays from 4-6pm, commencing January 9, 2009.
Place: BA 4164 (Bahen Building)
Place: BA 4164 (Bahen Building)
Course Syllabus
Readings
Information on the Course Paper
Click here for the slides from Dr. Kevin Chung's guest lecture on recent advances in technology mapping for FPGAs (3 April, 2009).
Assignments
Graphics package documentation (PDF)Graphics package source code
Assignment #1 -- Routing (PDF)
Test circuits for assignment #1
Assignment #2 -- Analytical Placement
Choose to do either part 1 (PDF) or part 2 (PDF) (you do not have to do both parts!)
Email the instructor on which you part you choose to do by February 16, 2009.
Part 1: May be done in pairs.
Part 2: Should be done individually.
Part 1: May be done in pairs.
Part 2: Should be done individually.
Part 1 files are here.
Part 2 files are here.
Assignment #3 -- Partitioning (PDF)
Test circuits for assignment #3
Exercises
Exercise #1 -- Annealing-Based Placement and Negotiated Congestion Routing (PDF)Exercise #2 -- Floorplanning by Mixed Integer Linear Programing (ILP) (PDF)
Text circuits: here
Exercise #3 -- Partitioning by the FM Heuristic (PDF)