ECE-1387: CAD for Digital Circuit Synthesis and Layout
Fall 2011NEWS:
- Thank you all for a terrific term!~ I really enjoyed teaching the class, and all the great discussion. (January 2012)
- Useful linear programming solver: http://lpsolve.sourceforge.net/5.5/
- E2 is posted (December 1, 2011)
- E1 is posted (November 21, 2011)
- A3 is posted (November 3, 2011)
- A2 is posted. (October 15, 2011)
- Test circuits for A1 are updated with new W values (as agreed in class). (October 7, 2011)
- A1 is extended by 1 week and is now due on October 14, 2011 in class. (October 4, 2011)
- All test circuits for A1 posted (Sept 27, 2011).
- Assignment #1 posted (Sept 21, 2011).
- Website created (Sept 9, 2011).
Basic Information
Instructor: Jason Anderson
E-mail: janders@eecg.toronto.edu
Web: http://www.eecg.toronto.edu/~janders
Tel: 416-946-7285
Office: EA 314 (Engineering Annex)
Instructor's Office hours: Email or phone for an appointment (or drop by my office)
Lectures: Fridays from 3:30-5:30 PM in BA 4164 (Bahen Building)
E-mail: janders@eecg.toronto.edu
Web: http://www.eecg.toronto.edu/~janders
Tel: 416-946-7285
Office: EA 314 (Engineering Annex)
Instructor's Office hours: Email or phone for an appointment (or drop by my office)
Lectures: Fridays from 3:30-5:30 PM in BA 4164 (Bahen Building)
Overview
The course covers the approaches and algorithms for
automatic circuit synthesis, with a concentration on the back-end of
the CAD flow. Topics covered will include: technology mapping,
partitioning, placement, routing, timing analysis, and physical
synthesis. The course will include experience with existing CAD tools
and building new tools in C. We will pay special attention to
synthesis issues as applied to Field-Programmable Gate Arrays (FPGAs).
Who should take this course?
The course will interest (at least!) three types of
students:
1) Students whose research falls in the area of computer-aided design for FPGAs or ASICs, or whose research pertains to the architecture of such chips.
2) Digital IC design engineers: it is important to know HOW the tools you use WORK!
3) Anyone interested in seeing some real/practical applications of combinatorial optimization algorithms.
1) Students whose research falls in the area of computer-aided design for FPGAs or ASICs, or whose research pertains to the architecture of such chips.
2) Digital IC design engineers: it is important to know HOW the tools you use WORK!
3) Anyone interested in seeing some real/practical applications of combinatorial optimization algorithms.
Course Syllabus and Lecture Schedule
Readings
Information on the Course Paper
Assignments
Two options for computer graphics:Simple X11 graphics (originally built by Vaughn Betz)
Graphics package documentation (PDF)
Graphics package source code
OR
Cairo-based graphics package (built by Xander Chin)
Xander welcomes feedback on the package (xan@eecg.toronto.edu)
Assignment #1: FPGA maze routing, with run-time optimization (PDF)
Test circuits
Assignment #2: Analytical Placement, net models, cell shifting schemes (PDF)
Test circuits
Linear system solver Getting started guide (PDF)
- Pages 2-3 of the guide shows an example that illustrates how to set-up the linear system and call the solver. The matrix is represented in a sparse form using 3 arrays: one holds the values in the matrix, one holds the column indices of the values, the last essentially encodes how many non-zero items are in each row of the matrix.
- NOTE: you do not need to use BLAS, as we are not optimizing for run-time. I believe the solver is easier to compile and use without worrying about BLAS. See install instructions on pages 4-5 of getting started manual (-DNBLAS option).
Test circuits
Exercises
Exercise #1: FM Partitioning (PDF)
Exercise #2: Simulated Annealing-Based Placement (PDF)
Code, documentation and circuits