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ECE 241 F - Digital Systems Fall
2008 |
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18-Aug-08 |
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Lecture, Lab and
Project Schedule |
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| Lect # |
Monday Date of
Week |
Contents |
Text
Chapter/Section |
Lab |
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| 1 |
1-Sep |
Motivation
- how this course fits into other ECE courses, Moore's Law/Transistor
Exponential Progres & course outline;
Handouts: basic, lab schedule, lab, CAD software, project |
1 |
No
Lab |
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| 2 |
7-Sep |
light
switches as logic functions, Variables & Functions,
truth tables; gates; basic AND/OR
NOT gates |
2.1
- 2.4 |
No Lab |
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| 3 |
simple
boolean expressions; sum of products form,
simple synthesis of logic - from truth tables; time-varying signals (timing
diagram); |
2.4,
2.6, 2.7 |
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| 4 |
Sum
of products representation & minterms; product-of-sums & maxterms;Lab 1 Discussion; including good practice in labs - bottom up
design, careful testing Voltage of logic levels, 7400 series logic family |
3.5.1,
2.5 |
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| 5 |
15-Sep |
Boolean
Algebgra, axioms,laws;
simple algebraic minimization; example; |
2.6,
4.1 |
Lab 1
- Combinational Logic, TTL, Protoboard |
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| 6 |
basic
multiplexor; How FPGAs are made |
2.8.2,
3.6.5 |
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| 7 |
Lab
2 Discussion: Intro to CAD; Intro to Verilog HDL language; Quartus software demo; |
2.9,
2.10 |
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| 8 |
22-Sep |
Making
circuits better: Optimization 1: 2, 3 & 4 variable Karnaugh maps |
4.1 |
Lab 2
- Using Computer Aided Design Tools to implement simple logic |
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| 9 |
Optimization
2 - product of sums,
Don’t cares |
4.3,
4.4 |
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| 10 |
Optimization
3 - optimization strategy & 7
segment example LAB
#3 discussion |
4.2,
6.4 |
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| 11 |
29-Sep |
Sequential
Logic; defn of comb. vs seq, Cross-coupled NOR latch, Transparency, RS Latch,
D Latch,
timing diagram; desire for edge trig; |
7.1,
7.2, 7.3 |
Lab 3
- Hierarchical Design of Logic Circuits |
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| 12 |
master-slave
D-type flip flop, timing diagram,
set up & hold time of FF; clock-to-Q; |
7.3.1,
7.4 |
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| 13 |
Serial
Transmission of Data - shift registers, parallel to serial conversion; Discuss LAB #4; Logic Analyzer |
7.8 |
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| 14 |
6-Oct |
Coding
Registers in Verilog ; |
7.12 |
Lab 4
- Latches, Flip-flops and Registers |
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| 15 |
Registers/Counters,
Ripple Counters, Synchronous Counter; BCD Counter; |
7.9-7.11 |
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| 16 |
Number
Representation and Signed Number Representation |
5.1-5.2 |
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| 17 |
13-Oct |
Numbers/Arithmetic
Representation, Adder - using basic logic, Full Adder, ripple carry adder |
5.1-5.2 |
Midterm! No Lab |
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| 18 |
2’s
complement addition and Subtraction - Lab 5 Discussion;
include LPMs - demo |
5.2-5.3 |
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| 19 |
State
Machine 1: intro; simple recognizer, steps-state diagram; method #1 - 1 one
encoding direct method
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8.1 |
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| 20 |
20-Oct |
State
Machine 2 - method #2 - full encoding, State Trans Table, K-map etc. |
8.2 |
Lab 5
- Adders, Registers and Counters |
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| 21 |
State
Machine 3: Lab 6 discussion - state machine for sequence recognition and
control of simple adder unit; LPMs,
handshaking big FSMs, FSM review |
8.4-8.5 |
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| 22 |
Verilog
coding of state machines, Project discussion |
8.4 |
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| 23 |
27-Oct |
General
form of Moore Machine, Example State
Machine design , |
8.5.2 |
Lab 6
- Finite State Machines; Project will need "uniqueness" signoff this week |
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| 24 |
Introduction
to memory (just how to interface to it) |
10.1.3 |
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| 25 |
Lab
7 Discussion - Hardware of displays, how to interface to to VGA controller
for Lab 7 |
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| 26 |
3-Nov |
RAM
- Static RAM; LPMs for SRAM; RAM as organized inside Cyclone FPGA; How to use
RAM |
10.1.3 |
Lab 7
- Video Graphics Array (VGA) Adapter; Project will need "scope" signoff this week |
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| 27 |
Internal
working of SRAM - bit, row, column; deocder (for address bus); tristate gate
(for data bus) |
10.1.4 |
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| 28 |
Debouncing
switches - different methods |
10.3.4 |
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| 29 |
10-Nov |
NMOS
transistor,NMOS &CMOS gates - build using transistors |
3.2,
3.3 |
Project
Period 1 |
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| 30 |
transistor
operation at process level; real propagation delay, waveform; fanout
dependency |
3.8.1
- 3.8.5 |
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| 31 |
Gate
Delay; critical path, maximum clock frequency; hold time violations; Flip
flop timing - setup and hold, clock to Q, Demo Quartus Timing Analyzer |
7.3.1,5.4,
7.15 |
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| 32 |
17-Nov |
Reading
delays from data sheets; Ring Oscillator |
Pg.
481, prob 7.30 |
Project
Period 2 |
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| 33 |
Fast
Addition: Carry-Lookahead Adder |
5.4 |
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| 34 |
Carry
Lookahead Addition, cont'd, Bit Serial Adder |
5.4 |
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| 35 |
24-Nov |
Space
left in schedule as buffer |
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Project
Period 3 |
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| 36 |
Multiplexors,
Multiplexors as Logic; Lookup Tables (LUTs) and LUT Mapping |
6.1,
6.2 |
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| 37 |
Shannon's
Expansion Theorem; |
6.1 |
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| 38 |
1-Dec |
Space
left in schedule as buffer |
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| 39 |
Course
Summary, Exam Discussion |
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