Field-Programmable Gate Arrays (FPGAs) have recently emerged as an attractive means of implementing logic circuits as a customized VLSI chip. FPGAs have gained rapid commercial acceptance because their user-programmability offers instant manufac turing turnaround and low costs. However, FPGAs are still relatively new and require architectural research before the best designs can be discovered. One area of particular importance is the design of an FPGA's routing architecture, which houses the user-pro grammable switches and wires that are used to interconnect the FPGA's logic resources. Because the routing switches consume significant chip area and introduce propagation delays, the design of the routing architecture greatly influences both the area utilization and speed-performance of an FPGA. FPGA routing architectures have already been stud ied using experimental techniques in [1] [2] and [3]. This paper describes a stochastic model that facilitates exploration of a wide range of FPGA routing architectures using a theoretical approach.
Stephen D. Brown, Jonathan Rose and Zvonko G. Vranesic, "A Stochastic Model to Predict the Routability of Field-Programmable Gate Arrays," IEEE Transactions on Computer Aided Design of Integrated Circuits and System, Vol 12, No. 12, Dec. 1993, pp 1827 - 1838.