List of Publications - Jonathan Rose

Graduate Theses

Projects

  1. The GILES/ATL Project Documents - Automated Layout of FPGAs from Architectural Specification

Patents

  1. V. Betz and J. Rose, "Automatic Generation of Programmable Logic Device Architectures," U.S. Patent # 6631510, Filed October 29, 1999, issued October 7, 2003. Delphion Patent Server Abstract PDF
  2. M. Khalid and J. Rose, "Multi-logic Device Systems Having Partial Crossbar and Direct Interconnection Architectures" U.S. Patent # 6604230, Filed February 9, 1999, issued August 5, 2003. Delphion Patent Server Abstract.
  3. V. Betz and J. Rose, "Heterogeneous interconnection architecture for programmable logic devices," U.S. Patent # 6590419, Filed October 12, 1999, issued July 8, 2003. Delphion Patent Server Abstract.
  4. S. Trimberger and J. Rose, "State Saving and Restoration in Reprogrammable FPGAS," U.S. Patent #5,844,422, filed November 13, 1996, issued Dec. 1, 1998. Delphion Patent Server Abstract.
  5. J. Rose and T. Bauer, "Logic BLock Structure Optimized for Sum Generation," U.S. Patent #5,724,276, filed June 17, 1996, issued March 3, 1998. Delphion Patent Server Abstract.
  6. J. Rose and V. Betz, "Complementary Architectures for Field-Programmable Gate Gate Arrays," U.S. Patent #5,537,341, filed February 10, 1995, issued July 16th, 1996 Delphion Patent Server Abstract.

Books

  1. V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, February 1999. ISBN 0-7923-8460-1. Read the text from the back cover of the book.

  2. S. Brown, R. Francis, J. Rose, Z. Vranesic, Field-Programmable Gate Arrays, Kluwer Academic Publishers, May 1992.

Journal Papers

  1. I. Kuon, R. Tessier and J. Rose "FPGA Architecture: Survey and Challenges", Foundations and Trends in Electronic Design Automation: Vol. 2: No 2, pp. 135-253.
  2. P. Yianancouras, J.G. Steffan and J. Rose, "Exploration and Customization of FPGA-Based Soft Processors," in IEEE Transactions on Computer-Aided Design, Vol. 26, No. 2, February 2007, pp. 266 - 277.
  3. I. Kuon and J. Rose, "Measuring the Gap between FPGAs and ASICs" in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, NO. 2, FEBRUARY 2007, pp. 203 - 215.
  4. A. Ye and J. Rose "Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOL. 14, NO. 5, May 2006, pp. 462-473.
  5. A. Ye and J. Rose "Measuring and utilising the correlation between signal connectivity and signal positioning for FPGAs containing multi-bit building blocks" in IEE Computer & Digital Techniques Journal Vol.153, No.3,pp.146-156, May 2006.
  6. A. Darabiha, J. Maclean and J. Rose, "Reconfigurable Hardware Implementation of a Phase-Correlation Stereo Algorithm," in Machine Vision and Applications Journal, Vol. 17. No 2., pp. 116-132, March 2006.
  7. Anish T. Alex, Michel Dumontier, Jonathan S. Rose, Christopher W. V. Hogue "Hardware-accelerated protein identification for mass spectrometry" Rapid Communications in Mass Spectrometry, Vol 19. No 6, March 30, 2005 PDF .
  8. P. Kundarewich and J. Rose, "Synthetic Circuit Generation Using Clustering and Iteration," in IEEE Trans. on Computer-Aided Design, Vol 23, No. 6, June 2004, pp. 869-887. PDF.
  9. E. Ahmed and J. Rose, "The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density," in IEEE Trans. on VLSI, Vol 12, No. 3, March 2004, pp. 288-298. PDF.
  10. M. Hutton, J. Rose and D. Corneil, "Automatic Generation of Synthetic Sequential Benchmark Circuits," in IEEE Trans. on CAD, Vol. 21, No. 8, August 2002, pp. 928-940 PDF.
  11. S. Wilton, J. Rose, Z. Vranesic, "Structural Analysis and Generation of Synthetic Digital Circuits with Memory," in IEEE Transactions on VLSI, Vol. 9, No. 1, February 2001, pp. 223-226 Postscript PDF.
  12. A. Marquardt, V. Betz, and J. Rose, "Speed and Area Trade-offs in Cluster-Based FPGA Architectures," in IEEE Transactions on VLSI, Vol. 8, No. 1, February 2000, pp. 84-93.
  13. M. Khalid and J. Rose, "A Novel and Efficient Routing Architecture for Multi- FPGA Systems," in IEEE Transactions on VLSI, February 2000, Vol. 8, No. 1, pp. 30-39. Postscript PDF.
  14. P. Chow, S. Seo, J. Rose, K. Chung, I Rahardja, and G. Paez, "The Design of an SRAM-Based Field-Programmable Gate Array: Part I: Architecture," in IEEE Transactions on VLSI, Vol. 7 No. 2, June 1999, pp. 191-197. Postscript PDF.
  15. P. Chow, S. Seo, J. Rose, K. Chung, I Rahardja, and G. Paez, "The Design of an SRAM-Based Field-Programmable Gate Array: Part II: Circuit Design and Layout," in IEEE Transactions on VLSI, Vol. 7 No. 3, Sept. 1999, pp. 321-330. Postscript PDF .
  16. M. Hutton, J. Rose, J. Grossman, and D. Corneil, "Characterization and Parameterized Generation of Synthetic Combinational Benchmark Circuits," in IEEE Trans. on CAD, Vol. 17, No. 10, October 1998, pp. 985-996. Postscript PDF.
  17. S. Wilton, J. Rose, Z. Vranesic, "The Memory/Logic Interface in FPGAs with Large Embedded Memory Arrays," in IEEE Trans. on VLSI. Vol. 7 No. 1, March 1999, pp. 80-91. Postscript PDF.
  18. V. Betz and J. Rose, "Effect of the Prefabricated Routing Track Distribution on FPGA Area-Efficiency," in IEEE Transactions on VLSI, Vol. 6, No. 3, Sept. 1998, pp. 445-456. Postscript PDF.
  19. D. Lewis, D. Galloway, M. van Ierssel, J. Rose, P. Chow, "The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System," in IEEE Transactions on VLSI, Vol. 6, No. 2, June 1998, pp 188-198. Postscript PDF .
  20. V. Betz and J. Rose, "How Much Logic Should Go in an FPGA Logic Block?", in IEEE Design & Test Magazine, Vol. 15, No. 1, Jan-March 1998, pp. 10-15. Postscript PDF .
  21. S. Brown and J. Rose, "FPGA and CPLD Architectures: A Tutorial," in IEEE Design and Test of Computers, Vol. 12, No. 2, Summer 1996, pp. 42-57. Postscript PDF.
  22. S. Brown, J. Rose, Z. Vranesic, "A Stochastic Model to Predict The Routability of Field-Programmable Gate Arrays," IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. 12, No. 12, December 1993, pp. 1827-1838. Postscript PDF.
  23. J. Rose, A. El Gamal, A. Sangiovanni-Vincentelli, "Architecture of Field-Programmable Gate Arrays," in Proceedings of the IEEE, Vol. 81, No. 7, July 1993, pp. 1013-1029.
  24. A. Sangiovanni-Vincentelli, A. El Gamal, J. Rose, "Synthesis Methods for Field-Programmable Gate Arrays," in Proceedings of the IEEE, Vol. 81, No. 7, July 1993, pp. 1057-1083.
  25. S. Singh, J. Rose, P. Chow, D. Lewis, "The Effect of Logic Block Architecture on FPGA Performance," IEEE JSSC, Vol. 27 No. 3, March 1992, pp. 281-287.
  26. S. Brown, J.S. Rose, Z. Vranesic, " A Detailed Router for Field Programmable Gate Arrays," IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. 11, No. 5, May 1992, pp. 620-628.
  27. J.S. Rose, S. Brown, " Flexibility of Interconnection Structures for Field-Programmable Gate Arrays ", IEEE JSSC Vol. 26 No. 3, March 1991, pp. 277-282.
  28. J.S. Rose, R.J. Francis, D. Lewis, and P. Chow, "Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency," IEEE JSSC, Vol. 25 No. 5, October 1990, pp. 1217-1225.
  29. J.S. Rose, "Parallel Global Routing for Standard Cells," IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. 9, No. 10, October 1990, pp. 1085-1095.
  30. J.S. Rose, W. Klebsch, J. Wolf, "Temperature Measurement and Equilibrium Dynamics of Simulated Annealing Placements," IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. 9, No. 3, March 1990, pp. 253-259.
  31. J.S. Rose, W.M. Snelgrove, Z.G. Vranesic, "Parallel Standard Cell Placement Algorithms with Quality Equivalent to Simulated Annealing," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 7, Number 3, March 1988, pp. 387-396.
  32. J.S. Rose, Z.G. Vranesic, W.M. Loucks, "FERMTOR: A Tunable Multiprocessor Architecture," IEEE MICRO, Vol. 5, No. 4, August 1985, pp. 5-17.

Refereed Papers in Conferences

  1. W-M. Fang and J. Rose "Modeling Routing Demand in Early-Stage FPGA Architecture Development," in ACM Symposium on FPGAs, February 2008, pp. 139-148.
  2. I. Kuon and J. Rose "Area and Delay Trade-offs in the Circuit and ArchitectureDesign of FPGAs," in ACM Symposium on FPGAs, February 2008, pp. 149-158.
  3. P. Jamieson and J. Rose, "Architecting Hard Crossbars on FPGAs and Increasing their Area-Efficiency with Shadow Clusters," in IEEE International Conference on Field Programmable Technology (FPT07), 2007, Kitakyushu, Japan, Decemeber 2007, pp. 57-64.
  4. P. Jamieson and J. Rose, "Enhancing the Area-Efficiency of FPGAs with Hard Circuits Using Shadow Clusters," in IEEE International Conference on Field Programmable Technology (FPT06), 2006, Bangkok, Thailand, Decemeber 2006, pp. 1-8.
  5. I. Kuon and J. Rose, "Measuring the Gap between FPGAs and ASICs," ACM Symposium on FPGAs, February 2006, pp. 21-30.
  6. P. Yiannacouras, J. G. Steffan and J. Rose, "Application Specific Customization of Soft Processor Microarchitecture" ACM Symposium on FPGAs, February 2006, pp. 201-210.
  7. P. Yiannacouras, J. Rose, and J. G. Steffan, "The Microarchitecture of FPGA-Based Soft Processors," International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES 2005), September 2005, San Francisco, CA, pp. 202-212.
  8. P. Jamieson and J. Rose, "A Verilog RTL Synthesis Tool For Heterogeneous FPGAs," in 2005 Int'l Conference on Field Programmable Logic and Applications (FPL'05), Tampere, Finland, August 2005, pp. 305-310.
  9. A. Ye and J. Rose, "Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks," in 2005 Int'l Conf. on Field Programmable Logic and Applications (FPL'05), Tampere, Finland, August 2005, pp 159-166.
  10. P. Jamieson and J. Rose, "Mapping Multiplexers onto Hard Multipliers in FPGAs," in the 3rd International IEEE Northeast Workshop on Circuits & Systems.
  11. I. Kuon, A. Egier and J. Rose, "Design, Layout and Verification of an FPGA using Automated Tools" in FPGA '05, ACM Symposium on FPGAs, February 2005, pp 215-226. PDF
  12. A.G. Ye, and J. Rose, "Using Bus-Based Connections to Improve Field-Programmable Gate Array Density for Implementing Datapath Circuits" in FPGA '05, ACM Symposium on FPGAs, February 2005, pp 3-13. PDF
  13. David Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David Galloway, Mike Hutton, Chris Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff and Jonathan Rose, "The Stratix II Logic and Routing Architecture" in FPGA '05, ACM Symposium on FPGAs, February 2005, pp 14-20. PDF
  14. A. Ye and J. Rose, "Using Multi-Bit Logic Blocks and Automated Packing to Improve Field-Programmable Gate Array Density for Implementing Datapath Circuits," in 2004 International Conference on Field Programmable Technology (FPT '04), December 2004, pp. 129-136. PDF
  15. A. Alex, J, Rose, R, Isserlin-Weinberger, C. Hogue, "Hardware Accelerated Novel Protein Identification," in Int'l Symp. on Field-Programmable Logic, Aug 2004, pp. 13-22. PDF .
  16. T. Czajkowski and J. Rose, "A Synthesis-Oriented Omniscient Manual Editor, " in FPGA '04, ACM Symposium on FPGAs, February 2004, pp 89-98. PDF
  17. J. Rose, "Hard vs. Soft: The Central Question of Pre-Fabricated Silicon," 34th International Symposium on Multiple-Valued Logic (ISMVL'04), May 2004, pp. 2-5 PDF .
  18. J. Fender and J. Rose, "A High-Speed Ray Tracing Engine Built on a Field-Programmable System," in IEEE International Conf. On Field-Programmable Technology, December 2003, pp. 188-195. PDF .
  19. P. Yiannacouras and J. Rose, "A Parameterized Automatic Cache Generator for FPGAs," in IEEE Int'l Conf. On Field-Programmable Technology, Dec. 2003, pp. 324-327. PDF .
  20. A. Ye, J. Rose and D. Lewis, "Architecture of Datapath-Oriented Coarse-Grain Logic and Routing for FPGAs," in IEEE CICC 2003, San Jose, CA, September 2003, pp. 61-64. PDF .
  21. A. Darabiha, J. Rose and W. J. MacLean "Video-Rate Stereo Depth Measurement on Programmable Hardware" Proceedings of the 2003 IEEE Computer Society Conference on Computer Vision & Pattern Recognition, June 1622, Madison, WI, Vol. 1, pp. 203-210. PDF . Slides .
  22. D. Lewis, V. Betz, D. Jefferson, A. Lee, C. Lane, P. Leventis, S. Marquardt, C. McClintock, B. Pedersen, G. Powell, S. Reddy, C. Wysocki, R. Cliff, and J. Rose, "The Stratix Routing and Logic Architecture" in FPGA '03, ACM. Symp. FPGAs, February 2003, pp. 15-20. PDF .
  23. K. Padalia, R. Fung, M. Bourgeault, A. Egier and J. Rose, "Automatic Transistor and Physical Design of FPGA Tiles From An Architectural Specification" in FPGA 2003, ACM Symp. FPGAs, Feburary 2003, pp. 164-172. PDF .
  24. A. Ye, J. Rose, D. Lewis "Synthesizing Datapath Circuits for FPGAs with Emphasis on Area Minimization", Proceedings of 2002 IEEE International Conference on Field-Programmable Technology", Hong Kong, December 2002, pp. 219-227 PDF .
  25. A. Roopchansingh and J. Rose, "Nearest Neighbour Interconnect Architecture in Deep Submicron FPGAs," IEEE Custom Integrated Circuits Conference, San Diego, CA, May 2002, pp. 59 - 62. PDF
  26. W. Chow and J. Rose, "EVE: A CAD Tool for Manual Placement and Pipelining Assistance of FPGA Circuits," in FPGA 2002, ACM Symp. FPGAs, Feburary 2002, pp. 85-94. PDF
  27. M. Sheng and J. Rose, "Mixing Buffers and Pass Transistors in FPGA Routing Architectures," in FPGA 2001, ACM Symp. FPGAs, Feburary 2001, pp. 75-84. Postscript PDF
  28. E. Ahmed and J. Rose, "The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density," in FPGA 2000, ACM Symp. FPGAs, February 2000, pp. 3-12. Postscript PDF
  29. V. Betz and J. Rose, "Automated Generation of FPGA Architectures," in FPGA 2000, ACM Symp. on FPGAs, February 2000, pp. 175-186 Postscript PDF .
  30. A. Marquardt, V. Betz, and J. Rose, "Timing-Driven Placement for FPGAs," in FPGA 2000, ACM Symp. on FPGAs, February 2000, pp. 203-213 Postscript PDF .
  31. V. Betz and J. Rose, ``Circuit Design, Transistor Sizing and Wire Layout of FPGA Interconnect,'' IEEE Custom Integrated Circuits Conference, San Diego, CA, May 1999, pp. 171 - 174. Postscript PDF
  32. V. Betz and J. Rose, "FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density," in FPGA `99, ACM Symp. on FPGAs, pp. 59-68. FPGA `99, ACM Symp. on FPGAs, Feb 1999, pp. 140-149. Postscript PDF.
  33. A. Marquardt, V. Betz, and J. Rose, "Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density," in FPGA `99, ACM Symp. on FPGAs, pp.37-46. Postscript PDF.
  34. Y. Sankar and J. Rose,"Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs" in FPGA `99, ACM Symp. on FPGAs, pp. 157-166. Postscript PDF
  35. J. Swartz, V. Betz and J. Rose, "A Fast Routability-Driven Router for FPGAs" in FPGA `98, ACM Symp. on FPGAs, Feb 1998, pp. 140-149. Postscript PDF.
  36. M. Khalid and J. Rose, "A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems," in FPGA `98, ACM Symp. on FPGAs, Feb 1998, pp. 45-54. Postscript PDF.
  37. V. Betz and J. Rose, "Cluster-Based Logic Blocks for FPGAs: Area-Efficiency vs. Input Sharing and Size," in IEEE CICC 1997, Santa Clara, CA, pp. 551-554. Postscript PDF.
  38. J. Rose and D. Hill, "Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond," in FPGA `97, ACM Symp. on FPGAs, Feb 1997, pp. 129-132 (invited) Postscript PDF.
  39. M. Hutton, J. Rose, D. Corneil, "Generation of Synthetic Sequential Benchmark Circuits," in FPGA `97, ACM Symp. on FPGAs, Feb 1997, pp. 149-155. Postscript PDF.
  40. S. Wilton, J. Rose, Z. Vranesic, "Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays," in FPGA `97, ACM Symp. on FPGAs, Feb 1997, pp. 10-16. Postscript PDF.
  41. D. Lewis, D. Galloway, M. van Ierssel, J. Rose, P. Chow, "The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System," in FPGA `97, ACM Symp. on FPGAs, Feb 1997, pp. 53-61. Postscript PDF.
  42. V. Betz and J. Rose, "Directional Bias and Non-Uniformity in FPGA Global Routing Architectures," in ICCAD 1996, pp. 652-659, November 1996. FPGA '95, pp. 10-16. Postscript PDF.
  43. M. Hutton, J.P. Grossman, J. Rose, D. Corneil, "Characterization and Parameterized Random Generation of Digital Circuits," in the 1996 Design Automation Conference, June, 1996, pp. 94-99. Postscript PDF.
  44. S. Wilton, J. Rose, Z. Vranesic, " Memory/Logic Interconnect Flexibility in FPGAs with Large Embedded Memory Arrays ," in CICC 96, the IEEE Custom Integrated Circuits Conf., San Deigo, CA, May 1996, pp. 144-147. Postscript PDF.
  45. T. Ngai, J. Rose, S. Wilton, " An SRAM-Programmable Field-Configurable Memory ," in CICC 95, the IEEE Custom Integrated Circuits Conf., Santa Clara, CA, May 1995, pp. 499-502. Postscript PDF.
  46. V. Betz, J. Rose, "Improving FPGA Performance via the Use of Architecture Families," 3rd ACM Intl Symposium on Field-Programmable Gate Arrays, FPGA '95, pp. 10-16. Postscript PDF.
  47. S. Wilton, J. Rose, Z. Vranesic, " Architecture of Centralized Field-Configurable Memory ," 3rd ACM Intl Symposium on Field-Programmable Gate Arrays, FPGA 95, pp. 97-103. Postscript PDF.
  48. D. Karchmer, J. Rose, "Definition and Solution of The Memory Packing Problem for Field-Programmable Systems," in the ACM/IEEE International Conference on Computer-Aided Design, ICCAD 94, pp. 20-26.
  49. J. He, J. Rose, "Advantages of Heterogeneous Logic Block Architectures for FPGAs," IEEE Custom Integrated Circuits Conf. 1993, (CICC 93), San Diego, May 1993 pp. 7.4.1 - 7.4.5. Postscript PDF
  50. P. Chow, S. Seo, K. Chung, G. Paez, J. Rose, "A High-Speed FPGA Using Programmable Mini-Tiles," in Symposium on Integrated Systems (formerly Conference on Advanced Research in VLSI), Washington, 1993, pp. 104-122.
  51. B. Fallah, J. Rose, "Timing-Driven Routing Segment Assignment in FPGAs," in the Canadian Conference on VLSI, CCVLSI 92, October 1992, pp. 124-130.
  52. B. Tseng, J. Rose, S. Brown, "Using Architectural and CAD Interactions to Improve FPGA Routing Architectures," in the IEEE, ICCD 92 October 1992, pp. 99 - 104. Postscript PDF
  53. K. Chung, J. Rose, "TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections," Proc. 29th ACM/IEEE Design Automation Conference, June 1992, Anaheim, CA, pp. 361-367.
  54. R.J Francis, J. Rose, Z. Vranesic, "Technology Mapping Lookup Table-Based FPGAs for Performance" Proc. 1991 IEEE International Conference on Computer-Aided Design (ICCAD), November 1991, pp. 568-571.
  55. R.J Francis, J. Rose, Z. Vranesic, "Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs," 28th ACM/IEEE Design Automation Conference, June 1991, pp. 227-233.
  56. S. Singh, J. Rose, D. Lewis, K. Chung, P. Chow "Optimization of Field-Programmable Gate Array Logic Block Architecture for Speed," in IEEE Custom Integrated Circuits Conference 91, CICC, May 1990, pp. 6.1.1 - 6.1.6.
  57. S. Brown, J.S. Rose, Z. Vranesic, "A Detailed Router for Field Programmable Gate Arrays" Proc. 1990 IEEE International Conference on Computer-Aided Design (ICCAD), pp. 382-385, November 1990. Designated as a distinguished paper.
  58. R.J Francis, J. Rose, K. Chung, "Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays," Proc. 27th ACM/IEEE Design Automation Conference, June 1990, pp. 613-619.
  59. J. Rose, S. Brown, "The Effect of Switch Box Flexibility on Routability of Field Programmable Gate Arrays," IEEE Proc. Custom Integrated Circuits Conference, (CICC), Boston May 1990, pp. 27.5.1 - 27.5.4.
  60. J.S. Rose, R.J. Francis, P. Chow, and D. Lewis, "The Effect of Logic Block Complexity on Area of Programmable Gate Arrays," Proc. IEEE Custom Integrated Circuits Conference, (CICC), San Diego, May 1989, pp. 5.3.1 - 5.3.5. Postscript PDF.
  61. J.S. Rose, W. Klebsch, J. Wolf, "Temperature Measurement of Simulated Annealing Placements," in IEEE International Conference on Computer-Aided Design, (ICCAD), November 1988, pp. 514-517.
  62. J.S. Rose, "The Parallel Decomposition and Implementation of an Integrated Circuit Global Router," ACM Sigplan Symposium on Parallel Programming: Experience with Applications, Languages and Systems, July 1988, pp. 138-145.
  63. J.S. Rose, "LocusRoute: A Parallel Global Router for Standard Cells," Proc. 25th Design Automation Conference, June 1988, pp. 189-195.
  64. J.S. Rose, D.R. Blythe, W. Snelgrove, Z. Vranesic, "Fast, High Quality VLSI Placement on an MIMD Multiprocessor," Proc. ICCAD 86, Nov. 1986, pp. 42-45.
  65. Z.G. Vranesic, J.S. Rose, W.M. Loucks, "A Flexible Architecture MIMD Supercomputer for Non-Numeric Applications," First International Conference on Supercomputing Systems, December 1985, pp. 455-459.
  66. J.S. Rose, W.M. Snelgrove, Z.G. Vranesic, "ALTOR: An Automatic Standard Cell Layout Program," 1985 Canadian Conference on Very Large Scale Integration, November 1985, pp. 169-173. This paper won a best paper award.

Refereed Presentations at Workshops

  1. M. Khalid and J. Rose, "Experimental Evaluation of Mesh and Partial Crossbar Routing Architectures for Multi-FPGA Systems," in IFIP IWLAS `97, Int'l Workshop on Logic and Architecture Synthesis, Grenoble, France, December 1997, pp. 119-127. Postscript PDF
  2. V. Betz and J. Rose, "VPR: A New Packing, Placement and Routing Tool for FPGA Research," in 7th International Workshop on Field-Programmable Logic, London, August 1997, pp. 213-222. Postscript PDF.
  3. M. Khalid and J. Rose, "The Effect of Fixed I/O Pin Positioning on The Routability and Speed of FPGAs," Proc. Canadian Workshop of Field-Programmable Devices, FPD 95, pp. 94-102. Postscript PDF.
  4. D. Galloway, D. Karchmer, P. Chow, D. Lewis, J. Rose, "The Transmogrifier: The University of Toronto Field-Programmable System," in the 1994 Canadian Workshop on Field-Programmable Devices. (formerly the CMC VLSI Workshop).
  5. J. He, J. Rose, "Technology Mapping for Heterogeneous FPGAs," in the ACM International Workshop on Field-Programmable Gate Arrays 1994, February 1994, FPGA '94. Postscript PDF.
  6. K. Chung, S. Singh, J. Rose, P. Chow, "Using Hierarchical Logic Blocks to Improve the Speed of Field-Programmable Gate Arrays," International Workshop on Field Programmable Logic and Applications, Sept 1991, Oxford, UK.
  7. P. Chow, S.O. Seo, D. Au, B. Fallah, C. Li, J.Rose, "A 1.2um CMOS FPGA Using Cascaded Logic Blocks and Segmented Routing," International Workshop on Field Programmable Logic and Applications, Sept 1991, Oxford, UK.
  8. J-M. Vuillamy, Z. Vranesic, J.Rose, "Performance Evaluation and Enhancement of FPGAs," International Workshop on Field Programmable Logic and Applications, Sept 1991, Oxford, UK.

Posters

  1. A. Alex, R. Isserlin-Weinberger, J. Rose and C. Hogue, "A Hardware Based Human Genome Database Search for Mass Spectrometry," 51st Annual American Society for Mass Spectrometry (ASMS)Conference on Mass Spectrometry and Allied Topics (June 8-12,2003).

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