Figure 4-a shows the effect of changing on the minimum track count required for 100% routability (averaged over 200 stochastically generated circuits). The results are shown for architectures with 2, 4, 8, and 16 two-kilobit blocks. The right-most point on each line corresponds to architectures with ; as discussed in Section 2, this is the maximum possible . As the graph shows, for architectures with fewer than 8 arrays, the measured minimum W is not sensitive to . This is contrast to  which shows that circuit routability for logic is severely hampered by low values of the connection block flexibility, .
As the number of memory arrays increases above 4, the number of tracks needed for complete routing does increase significantly for low ( is sufficient). There are several reasons for this. First, the circuits generated for these architectures tend to have larger memory requirements, and thus, use more memory pins (this is shown in Table 1). For small values of , the nets connected to each array have fewer routing options than nets connected to only logic elements. The more of these nets there are, the more sensitive the overall circuit routability will be to .
A second effect is from nets that connect to more than one memory array. Memory arrays are connected together when they are combined to form larger user memories, or when independent user memories share a common data bus. The more arrays in a circuit, the more of these memory-to-memory nets there are. The number of routing paths for these nets is very dependent on .
A final reason may be due to the way in which the memory connections are ``spread'' among the logic blocks, as determined by the parameter r. For architectures with only a few arrays, the value of r is significantly larger than for architectures with many arrays, as shown in Table 1, column 10. The higher r is, the more ``spread out'' the memory pins are. It is possible that a concentration of the low-flexibility memory pins in a single channel decreases routability.