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Circuit Delay

Although the main motivation behind using a small value of tex2html_wrap_inline363 was to reduce the area required for the memory/logic interconnect block, removing switches generally increases the speed of a circuit implemented on an FPGA. In this case, however, the memory/logic interconnect block does not represent a major portion of the critical path delay, so we would expect the speed to be roughly independent of tex2html_wrap_inline363 . Figure 4-c shows the average critical path delay of the 8 array architecture. As the graph shows, for low flexibilities, the delay actually drops slightly as tex2html_wrap_inline363 increases; this is because a low tex2html_wrap_inline363 often results in circuitous routes for some nets.

Steve Wilton
Thu Aug 1 15:28:50 EDT 1996