Although the main motivation behind using a small value of 
was to
reduce the area required for the memory/logic interconnect block, removing
switches generally increases the speed of a circuit implemented on an FPGA.
In this case, however, the memory/logic interconnect block does not
represent a major portion of the critical path delay, so we would expect the
speed to be roughly independent of . Figure 4-c
shows the average critical path delay of the 8 array architecture. As the
graph shows, for low flexibilities, the delay actually drops slightly as
increases; this is because a low often results in
circuitous routes for some nets.