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References
- 1
-
G. Feygin, P. Chow, P. G. Gulak, J. Chappel, G. Goodes, O. Hall, A. Sayes,
S. Singh, M. B. Smith, and S. Wilton, ``A VLSI Implementation of a Cascade
Viterbi Decoder with Traceback,'' in 1993 IEEE International Symposium
on Circuits and Systems, pp. 1945-1948, May 1993.
- 2
-
I. Agi, P. J. Hurst, and K. W. Current, ``A 450 MOPS image backprojector and
histogrammer,'' in IEEE 1992 Custom Integrated Circuits Conference,
pp. 6.2.1-6.2.4, May 1992.
- 3
-
R. Mason and K. Runtz, ``VLSI neural network system based on reduced
interchip connectivity,'' in Canadian Conference on Very Large Scale
Integration, pp. 7.69-7.74, Nov. 1993.
- 4
-
H. Satoh, T. Nishimura, M. Tatsuki, A. Ohba, S. Hine, and Y. Kuramitsu, ``A
209K-transistor ECL gate array with RAM,'' IEEE Journal of
Solid-State Circuits, vol. 24, pp. 1275-1279, Oct. 1989.
- 5
-
K. Kaneko, T. Okamoto, M. Nakajima, Y. Nakakura, S. Gokita, J. Nishikawa,
Y. Tanikawa, and H. Kadota, ``A VLSI RISC with 20-MFLOPS peak, 64-bit
floating point unit,'' IEEE Journal of Solid-State Circuits, vol. 24,
pp. 1331-1339, October 1989.
- 6
-
J. Rose, R. Francis, D. Lewis, and P. Chow, ``Architecture of programmable gate
arrays: The effect of logic block functionality on area efficiency,''
IEEE Journal of Solid-State Circuits, vol. 25, pp. 1217-1225, October 1990.
- 7
-
H.-C. Hsieh, W. S. Carter, J. Ja, E. Cheung, S. Schreifels, C. Erickson,
P. Freidin, L. Tinkey, and R. Kanazawa, ``Third-generation architecture
boosts speed and density of field-programmable gate arrays,'' in 1990
Custom Integrated Circuits Conference, pp. 31.2.1-31.2.7, 1990.
- 8
-
R. H. Krambeck, C. Chen, and R. Tsui, ``ORCA: A high speed, high density
FPGA architecture,'' in Compcon Spring '93, pp. 367-372, February
1993.
- 9
-
Crosspoint Solutions, Inc., CP20K Field Programmable Gate Arrays,
November 1992.
- 10
-
Plus Logic, FPSL5110 Product Brief.
- 11
-
D. E. Smith, ``Intel's FLEXlogic FPGA architecture,'' in Compcon
Spring '93, pp. 378-384, February 1993.
- 12
-
K. Kawana, H. Keida, M. Sakamoto, K. Shibata, and I. Moriyama, ``An efficient
logic block interconnect architecture for user-reprogrammable gate array,''
in IEEE 1990 Custom Integrated Circuits Conference, pp. 31.3.1-31.3.4,
May 1990.
- 13
-
T. Ngai, ``An SRAM-programmable field-reconfigurable memory,'' Master's
thesis, University of Toronto, 1994.
- 14
-
S. J. E. Wilton, Architecture of Field-Configurable Memory.
PhD thesis, University of Toronto, in progress.
- 15
-
S. J. E. Wilton and N. P. Jouppi, ``An access and cycle time model for on-chip
caches,'' Tech. Rep. 93/5, Digital Equipment Corporation Western Research
Lab, 1994.
- 16
-
J. M. Mulder, N. T. Quach, and M. J. Flynn, ``An area model for on-chip
memories and its application,'' IEEE Journal of Solid-State Circuits,
vol. 26, pp. 98-106, Feb. 1991.
Steve Wilton
Tue Jul 30 14:26:50 EDT 1996