FPGA Architecture Research - Jonathan Rose

• Basic Logic Block Architecture - the combinational and sequential functions of the logic block. Should the logic block be a two input NAND gate? NO![Rose90] It should usualy be something more coarse grained (bigger) because FPGA wires are expensive and slow, and so hooking up many small logic functions results in expensive and slow programmable logic. We have recently revisited this question, using much more modern CAD tools, architectural exploration methodologies and circuit modelling. While the original conclusions have not dramatically changed, some of the more favoured blocks are different, and the reasons for their superiority have changed. See [Ahmed00], as well as Elias Ahmed's Master's Thesis.


• Heterogenous Logic Block Architecture A key question in FPGA architecture, as FPGAs grow to tens of billions of transistors, is what differentiated functions should be in or besie the array? This could include full hard processors, arithmetic units, and memory (see below). It also could mean that there should be different kinds of soft logic blocks with different capabilities, as we first explored in [He93]. To be able to explore the utility of new kinds of blocks a more sophisticated CAD infrastructure that can synthesize, from an HDL level, into these structures needs to be created. We are working on this, in collaboration with colleagues from around the world.


• Memory has always been important in digital circuits, and we have looked at including memory inside FPGAs in a number of ways. First, as a standalone centralized memory: In [Wilton95], we studied the architecture of standalone memory and in [Ngai95], we built one. After that we looked at various aspects of the interconnection between distributed memory blocks in a programmable logic fabric: [Wilton96], [Wilton99], and [Wilton01].
  
  
• Cluster-based logic block architecture, in which several such basic logic elements are grouped into "fully-connected" groups have become important in recent years. We can show that certains sizes of clusters have superior area [Betz96] [Betz98] and performance [Marq99], as well as [Ahmed00].


• Basic Routing Architecture - the manner in which wires programmable switches are placed between the logic in order to make the programmable connections. At the beginning of research in this area, it was a not very well understood issue. The publications [Rose90] and [Rose91] were among the first to ask and answer the basic questions and create the basic terminology.


• The Global Routing Architecture dictates the quantity of wires present in "big" picture manner on the chip. For example, the global routing architecture could be that there are more tracks per channel on the periperhy of the chip than in the core, or vice-verse. It could also say that there are more horiztonal wires than vertical per channel. The work in [Betz96] and [Betz96] describes the advantages (and suprising lack thereof) many possible global routing architectures.


• The Detailed Routing Architecture of FPGAs has an strong effect on the speed performance of FPGAs, particularly as they are fabricated in deep-submicron processes. In particular the need for active buffers in the routing is now clear. However, buffers are not always needed, and so a key question is what proportion of the (necessarily prefabricated) routing resources should contain buffers? A related question is how long should the prefabricated wires be? This and many other questions are addressed in the book Architecture and CAD for Deep-Submicron FPGAs. A local description of the book can be found here . Also, a shorter version of some of the routing issues can be found in [Betz99a]. The paper [Betz99b] describes the electrical design necessary to realize these gains. The Altera Stratix routing architecture, described in [Lewis03] takes routing architecture several steps further, with a fully buffered architecture.
  
  We have also looked at issues dealing with the mixture of buffers and pass transistors in programmable routing [Sheng01] and issues dealing with nearest neighbour connectivity between logic blocks in an FPGA [Roopchansingh02].