The Transmogrifier-2 Field Programmable System

The Transmogrifier-2 Wins CMC Texpo Award for Novel Use of Microelectronic Components in the development of novel applications.

Introduction

The Transmogrifier-2 is a next-generation field-programmable system currently under construction at the University of Toronto. The goal of this project is provide a Field-programmable system with a usable logic capacity in excess of 2 Million gates.

What is the TM-2 Doing Right Now?

Click here to see the status of the Transmogrifier-2 - who is currently using it, the name of the program, and which boards and chips of the TM-2 are programmed. Please be patient, as this is a little bit slow for some strange WWW server reasons.

The Board

The TM-2 will consist of up to 16 boards, each of which contains:

Two Altera 10K100 FPGAs. These contain

4992 4-input lookup tables
12 blocks with 2K bits each of SRAM

four I-cube 320 programmable cross bar chips
more than 10Mbytes of RAM.

Here is a picture of the older version of the board, which uses Altera 10K50 FPGAs:

For a full-scale picture of the board, click the picture or here .

The System

The boards are connected by a backplane. The TM-2 has a novel inter-FPGA routing architecture (using the I-cubes crossbar chips) that gives routability in systems that scale from 2 boards up to 16 boards.

The latter system, with 16 boards would contain 32 Altera 10K100 FPGAs. This provides a nominal logic capacity of 100K x 32 = 3.2M gates. More realistically, counting only the lookup tables on the devices at 12 gates/LUT-FF pair, then a 16 board system yields 1.9M gates not including 768K bits of on-chip RAM.

Status

A 16 board Transmogrifier-2a system is now functioning and on-line. This is a full 2M gate system. You can find a picture of the new system here . Two video interface cards gave been built - one to take a camera as direcct input to the TM-2a, and one to generate video as direct output. Several applications have been run on a 2-board and 4-board system, including procedural texture mapping for wood, fire and marble. Also a video processor has been built that can do a number of video special effects. We're also currently working on a head tracking system as well as a video orbits . hardware implementation.

Papers and Documentation

These Postscript documents describe some of the details of the TM-2 and the support software:

A few overview slides describing the Transmogrifier-2 Architecture and Software
A paper that describes the architecture and some of the software of the TM-2: D. Lewis, D. Galloway, M. van Ierssel, J. Rose, P. Chow, "The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System," in FPGA `97, ACM Symp. on FPGAs, Feb 1997, pp. 53-61.
A longer, more recent version of the paper describing the TM-2, D. Lewis, D. Galloway, M. van Ierssel, J. Rose, P. Chow, "The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System," in submission.
An Example Application for the TM-2 is a step by step tutorial that tells you how to compile a simple example design, download it into the TM-2 and communicate with the design from a program on a UNIX workstation.
The manual for the Transmogrifier C language and compiler, which can be used to describe circuits for the TM-2.
The TM-2 Ports Package manual describes the library of routines that a C program can use to communicate with a design in the TM-2.
Creating and Running Circuits for the TM-2 describes the commands available for controlling and programming the TM-2.
The tm2mon Program describes the daemon that connects the TM-2 hardware to the network.

Working Application - Graphics Acceleration

We are currently using the TM-2 to develop graphics acceleration algorithms. The first project was to draw polygons. The second is to use a procedural texture mapping techniques to fill the polygons. Below we have two examples of a set of triangles that have been procedurally texture mapped, with some simple textures. Note that in actual operation, these triangles are bouncing around the screen.

A second example:

The People

The architecture of the board was developed by David Lewis , David Galloway, Marcus van Ierssel, Jonathan Rose , and Paul Chow , with some specification input from Michael Ayukawa, formerly of Nortel , now with Chip Express . The board was built by Marcus van Ierssel, and debugged with the aid of David Galloway. David Galloway wrote the software to do the above graphics acceleration.

Acknowledgements

Funding for this project has come from NSERC , Micronet , Altera , Nortel , ATI , and Ricoh .
Support, in the form of equipment contributions from Altera , Cypress Semiconductor , and I-cube are gratefully acknowledged.

Research on FPGAs at the University of Toronto.

Return to Jonathan Rose's Page .Computer Group.