CCirc and CGen

Clustered And Iterative Synthetic Circuit Generation

CCirc is a tool for characterizing the properties of circuits, while CGen is a tool for generating synthetic circuits.
These tools were written to help alleviate a shortage of benchmark circuits used in the testing and design of
CAD tools and FPGA architectures.

CCirc takes as input a circuit in the BLIF netlist format (soonVHDL and Verilog) and outputs statistical information.
CGen takes as input statistical information about a circuit and outputs netlists in BLIF or VHDL (soon Verilog)
ready to be place and routed by a tool such as VPR.

These two tools derive from initial work by Mike Hutton on synthetic circuit generation and incorporate new clustering and
iterative generation techniques. More information of the Synthetic Circuit Generation project can be found here.

Executables are available for Linux, Solaris, and Windows and source code is provided for those who want to modify the code or for those who want to compile for other platforms.

Click here to download the source, documentation, and executables for CCirc and CGen.

Click here to download my M.A.Sc. thesis that describes the algorithms used in CCirc and CGen.

Click here to download a number of circuit characterizations that can be used as input into CGen.

Finally, if you plan on using in your research, please mail paul.kundarewich@utoronto.ca so that I can keep track of who is using CCirc and CGen and inform you of updates as they become available.