Generation Report - DDR2 SDRAM High Performance Controller v8.0 |
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| Entity Name | ddr2_24x8_8_controller_phy | | Variation Name | ddr2_24x8_8 | | Variation HDL | Verilog HDL | | Output Directory | /autofs/jayar/b/b5/weizer/public_www/LUgen/upload/ddr2_24x8_8 |
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File SummaryThe MegaWizard interface is creating the following files in the output directory: |
| File | Description |
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| ddr2_24x8_8.v | A MegaCore® function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software. | | ddr2_24x8_8_bb.v | Verilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design. | | ddr2_24x8_8.qip | Contains Quartus II project information for your MegaCore function variation. | | ddr2_24x8_8.html | The MegaCore function report file. |
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MegaCore Function Variation File Ports| Name | Direction | Width |
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| local_address | INPUT | 24 | | local_write_req | INPUT | 1 | | local_read_req | INPUT | 1 | | local_ready | OUTPUT | 1 | | local_rdata | OUTPUT | 16 | | local_rdata_valid | OUTPUT | 1 | | local_wdata | INPUT | 16 | | local_be | INPUT | 2 | | local_size | INPUT | 2 | | reset_request_n | OUTPUT | 1 | | mem_odt | OUTPUT | 1 | | mem_clk | BIDIR | 1 | | mem_clk_n | BIDIR | 1 | | mem_cs_n | OUTPUT | 1 | | mem_cke | OUTPUT | 1 | | mem_addr | OUTPUT | 13 | | mem_ba | OUTPUT | 2 | | mem_ras_n | OUTPUT | 1 | | mem_cas_n | OUTPUT | 1 | | mem_we_n | OUTPUT | 1 | | mem_dq | BIDIR | 8 | | mem_dqs | BIDIR | 1 | | mem_dqsn | BIDIR | 1 | | mem_dm | OUTPUT | 1 | | local_refresh_ack | OUTPUT | 1 | | local_wdata_req | OUTPUT | 1 | | local_init_done | OUTPUT | 1 | | reset_phy_clk_n | OUTPUT | 1 | | oct_ctl_rs_value | INPUT | 14 | | oct_ctl_rt_value | INPUT | 14 | | global_reset_n | INPUT | 1 | | pll_ref_clk | INPUT | 1 | | phy_clk | OUTPUT | 1 | | aux_full_rate_clk | OUTPUT | 1 | | aux_half_rate_clk | OUTPUT | 1 | | soft_reset_n | INPUT | 1 |
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