Generation Report - ALTMEMPHY v8.0

Entity Nameddr2_25x16_4_phy_alt_mem_phy_siii
Variation Nameddr2_25x16_4_phy
Variation HDLVerilog HDL
Output DirectoryC:\Wei\research\project\release

File Summary

The MegaWizard interface is creating the following files in the output directory:
FileDescription
ddr2_25x16_4_phy.vA MegaCore® function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.
ddr2_25x16_4_phy_bb.vVerilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design.
ddr2_25x16_4_phy.qipContains Quartus II project information for your MegaCore function variation.
ddr2_25x16_4_phy.htmlThe MegaCore function report file.

MegaCore Function Variation File Ports

NameDirectionWidth
pll_ref_clkINPUT1
global_reset_nINPUT1
soft_reset_nINPUT1
reset_request_nOUTPUT1
phy_clkOUTPUT1
reset_phy_clk_nOUTPUT1
aux_half_rate_clkOUTPUT1
aux_full_rate_clkOUTPUT1
local_addressINPUT25
local_read_reqINPUT1
local_wdataINPUT32
local_write_reqINPUT1
local_sizeINPUT2
local_beINPUT4
local_refresh_reqINPUT1
local_burstbeginINPUT1
local_readyOUTPUT1
local_rdataOUTPUT32
local_rdata_validOUTPUT1
local_init_doneOUTPUT1
local_refresh_ackOUTPUT1
local_wdata_reqOUTPUT1
ctl_addressOUTPUT25
ctl_read_reqOUTPUT1
ctl_wdataOUTPUT32
ctl_write_reqOUTPUT1
ctl_sizeOUTPUT2
ctl_beOUTPUT4
ctl_refresh_reqOUTPUT1
ctl_burstbeginOUTPUT1
ctl_readyINPUT1
ctl_wdata_reqINPUT1
ctl_rdataINPUT32
ctl_rdata_validINPUT1
ctl_refresh_ackINPUT1
ctl_mem_addr_hINPUT13
ctl_mem_addr_lINPUT13
ctl_mem_ba_hINPUT2
ctl_mem_ba_lINPUT2
ctl_mem_cas_n_hINPUT1
ctl_mem_cas_n_lINPUT1
ctl_mem_cke_hINPUT1
ctl_mem_cke_lINPUT1
ctl_mem_cs_n_hINPUT1
ctl_mem_cs_n_lINPUT1
ctl_mem_odt_hINPUT1
ctl_mem_odt_lINPUT1
ctl_mem_ras_n_hINPUT1
ctl_mem_ras_n_lINPUT1
ctl_mem_we_n_hINPUT1
ctl_mem_we_n_lINPUT1
ctl_mem_beINPUT4
ctl_mem_dqs_burstINPUT1
ctl_mem_wdataINPUT32
ctl_mem_wdata_validINPUT1
ctl_mem_rdataOUTPUT32
ctl_mem_rdata_validOUTPUT1
ctl_rlatOUTPUT6
ctl_init_doneINPUT1
ctl_doing_rdINPUT1
ctl_add_1t_ac_latINPUT1
ctl_add_1t_odt_latINPUT1
ctl_add_intermediate_regsINPUT1
ctl_negedge_enINPUT1
ctl_usr_mode_rdyOUTPUT1
mem_addrOUTPUT13
mem_baOUTPUT2
mem_cas_nOUTPUT1
mem_ckeOUTPUT1
mem_cs_nOUTPUT1
mem_dmOUTPUT4
mem_odtOUTPUT1
mem_ras_nOUTPUT1
mem_we_nOUTPUT1
mem_reset_nOUTPUT1
mem_clkBIDIR1
mem_clk_nBIDIR1
mem_dqBIDIR16
mem_dqsBIDIR4
mem_dqsnBIDIR4
resynchronisation_successfulOUTPUT1
postamble_successfulOUTPUT1
tracking_successfulOUTPUT1
tracking_adjustment_upOUTPUT1
tracking_adjustment_downOUTPUT1
dqs_delay_ctrl_importINPUT6
dqs_delay_ctrl_exportOUTPUT6
dll_reference_clkOUTPUT1
pll_reconfig_enableINPUT1
pll_reconfig_counter_typeINPUT4
pll_reconfig_counter_paramINPUT3
pll_reconfig_data_inINPUT9
pll_reconfig_read_paramINPUT1
pll_reconfig_write_paramINPUT1
pll_reconfigINPUT1
pll_reconfig_clkOUTPUT1
pll_reconfig_resetOUTPUT1
pll_reconfig_data_outOUTPUT9
pll_reconfig_busyOUTPUT1
oct_ctl_rs_valueINPUT14
oct_ctl_rt_valueINPUT14
local_autopch_reqINPUT1
local_powerdn_reqINPUT1
local_self_rfsh_reqINPUT1
local_self_rfsh_ackOUTPUT1
local_powerdn_ackOUTPUT1
ctl_autopch_reqOUTPUT1
ctl_powerdn_reqOUTPUT1
ctl_self_rfsh_reqOUTPUT1
ctl_self_rfsh_ackINPUT1
ctl_powerdn_ackINPUT1