Generation Report - DDR2 SDRAM High Performance Controller v8.0

Entity Nameddr2_24x32_8_controller_phy
Variation Nameddr2_24x32_8
Variation HDLVerilog HDL
Output DirectoryC:\Wei\research\project\release\CoreLib\ddr2_24x32_8

File Summary

The MegaWizard interface is creating the following files in the output directory:
FileDescription
ddr2_24x32_8.vA MegaCore® function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.
ddr2_24x32_8_bb.vVerilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design.
ddr2_24x32_8.qipContains Quartus II project information for your MegaCore function variation.
ddr2_24x32_8.htmlThe MegaCore function report file.

MegaCore Function Variation File Ports

NameDirectionWidth
local_addressINPUT24
local_write_reqINPUT1
local_read_reqINPUT1
local_readyOUTPUT1
local_rdataOUTPUT64
local_rdata_validOUTPUT1
local_wdataINPUT64
local_beINPUT8
local_sizeINPUT2
reset_request_nOUTPUT1
mem_odtOUTPUT1
mem_clkBIDIR1
mem_clk_nBIDIR1
mem_cs_nOUTPUT1
mem_ckeOUTPUT1
mem_addrOUTPUT13
mem_baOUTPUT2
mem_ras_nOUTPUT1
mem_cas_nOUTPUT1
mem_we_nOUTPUT1
mem_dqBIDIR32
mem_dqsBIDIR4
mem_dqsnBIDIR4
mem_dmOUTPUT4
local_refresh_ackOUTPUT1
local_wdata_reqOUTPUT1
local_init_doneOUTPUT1
reset_phy_clk_nOUTPUT1
oct_ctl_rs_valueINPUT14
oct_ctl_rt_valueINPUT14
global_reset_nINPUT1
pll_ref_clkINPUT1
phy_clkOUTPUT1
aux_full_rate_clkOUTPUT1
aux_half_rate_clkOUTPUT1
soft_reset_nINPUT1