As the logic and computational capacity of FPGAs have grown, FPGAs have become an attractive platform for accelerating many computations including scientific applications. The high level of parallelism and abundant flexibility available in the FPGA fabric offer the promise of significant speed-up. However, adoption of using FPGA as accelerators by the scientific computing community has been limited because the creation of an FPGA design is difficult and time consuming and outside the skill set of the typical scientific computing user. In addition, once a design has been created for one specific FPGA chip and board, the same design cannot be easily transferred to another. The design is locked onto that FPGA-based platform because it typically has a specific memory architecture that soon becomes outdated.
In contrast, software is highly portable. Once a software application is completed, it can easily be upgraded to new and faster machines and obtain significantly better performance. This permits software programmers to develop and maintain rich libraries that solve important problems. Scientific computing users need not be highly skilled in creating optimized code because they can simply use the functions in these libraries. In hardware, IP cores do allow some design reuse, but at a much lower level of abstraction than with high level software libraries.
We present a solution for making FPGA-based computation more accessible by creating a computational “library” that is portable to any FPGA platform with minimal effort. The key second feature of the library is that its performance should also scale with the capabilities and resources of the FPGA. Given an FPGA with more capacity and faster elements, the library performance should improve without extra effort from the designer. By creating a portable and scalable library, we can drastically reduce the development cost and increase the life span of the design, thus making it more attractive to scientific computing users.
The generator can control the amount of resources that can be used on the FPGA allowing for various sized hardware designs that can be used as benchmarks for FPGA architecture exploration.