Exceptions Support

The supersmall soft processor implements the following standard MIPS-I exceptions:

Number Mnemonic Description
0IntExternal Interrupt
4AdELAddress Error Exception (Load or instruction fetch)
5AdESAddress Error Exception (Store)
8SysSYSCALL Exception
9BpBreakpoint Exception
10RIReserved Instruction Exception
11CpUCo-Processor Unusable Exception
12OvfArithmetic Overflow Exception

Coprocessor Registers

The following coprocessor registers are implemented, with the specified fields. All other fields are permanent don't care values, and non-writeable. Access to these registers is enabled using the mfc0 and mtc0 instructions.

BadVAddr Register (#8)

This register holds the value of the address that caused an AdEL or AdES exception. All 32 bits are used to hold this address. Read-only.

Status Register (#12)

Status register

This register controls whether or not interrupts are enabled. Bits 15-8 contain an interrupt mask, and bits 4, 2, and 0 contain a three-way stack for the interrupt enable bit. Read-write.

Cause Register (#13)

Cause register

This register contains information about the cause of an interrupt or exception. Bit 31 shows whether or not the current exception occured within a branch delay slot. Bits 29-28 show which coprocessor has errored in the event of a coprocessor error. Bits 15-8 show any pending interrupts. Bits 6-2 give the exception code uniquely identifying the cause of the exception, as encoded by the above table. Bits 9-8 are writeable by software (and therefore, not by hardware).

EPC Register (#14)

This register gives the address of the instruction at which the exception occurred. This instruction has not yet been executed by the processor. All 32 bits are used to hold this address. Read-only.

Events occurring on exception/interrupt

Implementation Quirks