Exceptions Support
The supersmall soft processor implements the following standard MIPS-I exceptions:
| Number | Mnemonic | Description |
|---|---|---|
| 0 | Int | External Interrupt |
| 4 | AdEL | Address Error Exception (Load or instruction fetch) |
| 5 | AdES | Address Error Exception (Store) |
| 8 | Sys | SYSCALL Exception |
| 9 | Bp | Breakpoint Exception |
| 10 | RI | Reserved Instruction Exception |
| 11 | CpU | Co-Processor Unusable Exception |
| 12 | Ovf | Arithmetic Overflow Exception |
Coprocessor Registers
The following coprocessor registers are implemented, with the specified fields. All other fields are permanent don't care values, and non-writeable. Access to these registers is enabled using the mfc0 and mtc0 instructions.
BadVAddr Register (#8)
This register holds the value of the address that caused an AdEL or AdES exception. All 32 bits are used to hold this address. Read-only.
Status Register (#12)
This register controls whether or not interrupts are enabled. Bits 15-8 contain an interrupt mask, and bits 4, 2, and 0 contain a three-way stack for the interrupt enable bit. Read-write.
Cause Register (#13)
This register contains information about the cause of an interrupt or exception. Bit 31 shows whether or not the current exception occured within a branch delay slot. Bits 29-28 show which coprocessor has errored in the event of a coprocessor error. Bits 15-8 show any pending interrupts. Bits 6-2 give the exception code uniquely identifying the cause of the exception, as encoded by the above table. Bits 9-8 are writeable by software (and therefore, not by hardware).
EPC Register (#14)
This register gives the address of the instruction at which the exception occurred. This instruction has not yet been executed by the processor. All 32 bits are used to hold this address. Read-only.
Events occurring on exception/interrupt
- IEo = IEp
- IEp = IEc
- IEc = 0
- BD bit set
- CE bits set (undefined if not a coprocessor exception)
- ExcCode set
- EPC register set to address of aborted instruction
- BadVaddr register set (undefined if not an AdEL/AdES exception)
- Program counter set to 0x04000180
Implementation Quirks
- Due to the supersmall's Harvard architecture, if you want instruction memory to be addressable, you need to map it to the data memory interface using SOPC builder.
- There is no PRId register by default. (If you need one, you can uncomment a line in cop0serial.v).
- There is no AdEL exception on an invalid instruction fetch. All instruction fetches on the supersmall are by definition aligned.