edif2blif is a utility that converts files from the industry-standard EDIF format to Berkeley's BLIF format, used extensively in academic tools. This utility is currently being used to convert circuits designed in VHDL or AHDL to BLIF by compiling them in Altera MaxPlus2 and saving as an EDIF netlist. These circuits will be added to our set of benchmark circuits and are currently being used to test our place and route tools for FPGAs.
To learn more about the features of edif2blif, please download the user documentation in Postscript or Portable Document Format.
If you would like to download edif2blif, please fill out the following information and click on "Download."