FPGA CAD Software From the Toronto FPGA Research Group

Front End Synthesis for FPGAs

• Odin - A Front-End Elaborator and Partial Mapper for Heterogenous FPGAs
  
  

Placement and Routing

• VPR and VPack Version 5.0 Beta: Major New (Beta) Release of VPR that supports Single Driver Routing, Heterogeneous Logic, and Optimized Architecture files across a wide range of architectures and processes and Area-Speed Tradeoffs .
  
  
• FPGA Placement and Routing Challenge!
  
  
• VPR and VPack Version 4.30 : Versatile Packing, Placement and Routing for FPGAs .
  
  
• CGE-A Detailed Router for Symmetric FPGAs - not oriented to Segmentation
  
  
• SEGA-A Detailed Router for Symmetric FPGAs, Segmented-Oriented
  
  
• PGAROUTE-A Global Router for Symmetric FPGAs

Synthetic Digital Circuit Benchmark Generation and Characterization of Digital Circuits

• CCIRC and CGEN - Next Generation Synthetic Circuit Generation
  
  
• CIRC and GEN - Characterization and Quality Random Digital Circuit Generation

Hardware Core Generators

• Cachegen - Automatic Parameterized Cache Generation for Stratix FPGAs

Hardware Description Language Synthesis for FPGAs

• Subset C Hardware Description Language and Compiler (C to XNF) - Transmogrifier C

Technology Mapping

• Chortle-Technology Mapping for Lookup Tables (ZIP File)

Graphics Package - Easy GL by Vaughn Betz and William Chow

• Easy GL Graphics Package for the PC .
  
  

Variable Serial Data Width Arithmetic Module Generation

• PSAC - A Variable Serial Data Width Arithmetic Module Generator .
  
  

EDIF to BLIF Converter

• EDIF to BLIF Converter.