VPR is an FPGA Placement and Routing tool developed at the University of Toronto. It has become the de facto standard in academic research and is one of the most cited tools in FPGA literature. In 2007-2008, VPR underwent a significant release supporting many modern features that are common in commercial FPGA chips. I'm one of the developers for the continued maintenance and development of VPR.

For more information on VPR, please visit: http://www.eecg.utoronto.ca/vpr

*New* The Verilog-to-Routing (VTR) CAD flow project for FPGA architecture exploration has entered open beta. You can try out this new flow here: http://www.eecg.utoronto.ca/vtr