ECE334S - Digital Electronics - Spring 2010

General

This course is an introduction to building digital integrated circuits with emphasis on the transistor level aspects of IC design. Topics to be covered are CMOS logic design, integrated circuit processing, layout design, transistor sizing, combinational circuit design, sequential logic, power dissipation, crossing clock domains, memory circuits, and I/O circuits.

This page can also be accessed directly at http://www.eecg.toronto.edu/~johns/ece334/ece334.html

Announcements

Feb 4 Fixed an error on equation sheet

Feb 4 Problem set 3 assigned. (Note some questions were on problem set 2b)

Feb 2 Added tutor names and emails

Feb 1 Equation sheet 01 for term test 1 posted under grades/tests

Jan 29 Problem set 2b assigned. To be taken up in Feb 2/Feb 5 tutorials

Jan 22 Problem set 2 assigned. To be taken up in Jan 26/Jan 29 tutorials.

Jan 14 Problem Set 1 assigned. To be taken up in Jan 19/Jan 22 tutorials.

Jan 5 Tutorial schedule posted

Nov 11 Course web page goes live!

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Lecturer

David A. Johns Email: johns@eecg.toronto.edu Office: BA5144 (inside of BA5145)

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Textbook

"CMOS VLSI Design" (third edition) by N.H. E. Weste and D. Harris, Addison Wesley, 2005 ISBN: 0-321-14901-7

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Lectures

Monday 1-2pm BA1170

Thursday 1-2pm BA1180

Friday 2-3pm BA1180

Lec #	Topic	Textbook Section	Lecture Notes
	Introduction	1.1, 1.2	Intro.pdf
	CMOS logic	1.3-1.4	cmos_logic_intro.pdf
	CMOS logic	1.4
	CMOS logic	1.4
	CMOS Layout	1.5	Layout.pdf
	Ideal MOS transistors	2.1, 2.2	mos_transistors.pdf
	Simple MOS Capacitance	2.3
	Detailed MOS Capacitance	2.3
	Non-ideal effects	2.4	non_ideal_mos_effects.pdf
	Non-ideal effects	2.4
	DC Transfer Characteristics	2.5	inverter_dc_analysis.pdf
	DC Transfer Characteristics	2.5
	Delay Estimation	4.2	delay estimation.pdf
	Delay Estimation	4.2
	Transistor sizing	4.2
	Review Lecture	4.2
	Unit Delay and Inverter Chain Sizing	4.2,4.3	inverter_chain_sizing.pdf
	Dynamic Power Dissipation	4.4
	Dynamic Power Dissipation	4.4	Dynamic Power.pdf
	CMOS Processing	3.2	processing.pdf
	CMOS Processing	3.2	Silicon Run Video
	Elmore Delay	4.2	Elmore_Delay.pdf
	Interconnect Delay	4.5	Interconnect.pdf
	Schmitt Trigger Circuits		Schmitt.pdf
	Circuit Families: Static CMOS, Ratioed	6.2.1, 6.2.2
	Circuit Families: CVSL, Dynamic	6.2.3, 6.2.4
	Sequential Circuit Design	7.2
	Register Circuits, setup and hold timing	7.3	Register_setup_hold.pdf
	Synchronizers	7.6	metastability.pdf
	Synchronizers	7.6
	Memory Intro	11.1	memory_01.pdf
	SRAM memory	11.2
	SRAM memory	11.2	memory_02.pdf
	DRAM memory	11.3
	ROM memory	11.4
	EEPROM,Flash memory		memory_03.pdf
	IC Packaging	12.2	packaging.pdf
	Power Distribution	12.3	power_distribution.pdf
	Clock Design	12.5	clock_design.pdf
	Review Lecture