ECE334---Problem answers

Chapter 2 
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1. a) I_D=900 uA
   b) V_D=0.65V, I_D=922uA
   d) V_D=0.77V, I_D=863uA and V_D=0.764, I_D=0.868uA

2. a) I_D=0, V_D=3.3V
   b) Reverse
   c) 110.75e-6 cm
   d) 1.12fF
   e) New voltage reduces reverse bias voltage -> less depletion width
      -> more capacitance similar to plates being closer together.

3. tau=4ns, t_sat=11.2ns

4. a) NMOS: active  PMOS: cutoff
   b) NMOS: triode  PMOS: active
   c) NMOS: cutoff  PMOS: triode

7. (plots)

10. a) depletion, NMOS, V_T<0
    c) K=63.9uA/V^2, V_To=-1.2V, lambda=0.07 V^-1

13. a) (plot)

Chapter 3
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1. V_OL=0.57V, V_OH=4.86V, V_IL=2V, V_IH=3V, NM_H=1.86V, NM_L=1.43V

2. a) non-inverting buffer
   b) (plot)
   c) marginally regenerative, Rin(low)=inf, Rin(high)=2.26k, 
      Rout(low)=800, Rout(high)=1k
   d) Vin=0: 6.36mW, Vin=3V: 7.95mW

4. a) W_n=4.8um, L_n=1.2um, W_p=2.4um, L_p=1.2um
   b) V_OH=5V, V_OL=0V, V_m=1.7V, V_IH=1.89V, V_IL=1.17V
   c) Fanout has no effect.
   d) (SPICE)

5. W_p=2.4um, W_n=9um, V_m=1.49V, NM_L decreases, NM_H increases

11. a) Cgd1=1.55fF, Cgd2=4.65fF, Cg3=3.8fF, Cg4=11.4fF
       C_w=2fF, Cdb1LH=6.3fF, Cdb2LH=4.3fF, Cdb1HL=4.12fF, Cdb2HL=6.56fF
    b) C_LLH=34fF, C_LHL=34.1fF
    c) t_pHL=422ps, t_pLH=422ps
    d) fan out <= 8

12. a) t_pLH=155ns, t_pHL=10.1ns, t_p=82.5ns
    b) t_pLH >> t_pHL
    c) Vin=V_OL: 0mW, Vin=V_OH: 0.316mW, dynamic: 0.86mW

Chapter 4
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2. a) Yes, F= (ABCD+E)bar
   b) Yes.
   c) No, capacitances are different

4. a) (W/L)_s = ((L/W)_1 + (L/W)_2)^-1
   b) (W/L)_p = (W/L)_1 + (W/L)_2

5. exclusive NOR, A is dual network, Yes, B is valid.

14. a) t_pLH=t_pHL = 235ps
    b) 50uW

15. a) 3.47
    b) Introduce buffer every 5 stages

Chapter 6
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1. b) Yes, J=1 glitch is caught

11. a) V_OH=5V, V_OL=0.23V
    b) V_M+=3V, V_M-=2.13V

12. V_OH=5V, V_OL=0.01V, V_M+=2.16V, V_M-=1.75V

13. c) C=3.62nF
    d) 150.6us 

14. a) astable
    b) t_3-t_2= -RC*ln((V_M+ - Vdd)/V_M- - Vdd)
       t_2-t_1= -RC*ln(V_M- / V_M+)
       T_osc = t_3 - t_1

15. For V_Z, T_hi = 900ns, T_low = 300ns, f=833.33kHz