The following topics are potential project topics. 
Some of the projects imply having access to some of the tools in eecg.
If you do not have access to the eecg machines, you won't be able to do those projects. 

1) Implement one of the circuits in PREP Benchmarks in both Altera 
CPLDs and FPGAs using 2 methods: VHDL and schematic. 
Then compare the capacity and the speed of each possible implementations 
(schematic in CPLD, schematic in FPGA, VHDL in FPGA, VHDL in CPLD). 
Provide a discussion as to why you beleive the results turn out as they do.
I have only one copy of PREP Benchmarks, you may borrow and copy the info 
regarding your choice of the circuit.

2) Implement one of the following circuits in both FPGAs and CPLDs using VHDL.
 Then compare the speed and area-efficiency of your implementation. 
For larger designs you don't have to do both FPGA and CPLD implementation.

- inverse DCT
- FIR  
- IIR
- Encryption algorithms (IDEA or DES)
- MPEG or JPEG (part of the whole thing - maybe in groups of 2)
- PCI slave/ Master (simplified PCI is acceptable)
 
3) In this web page http://www.altera.com/html/mktg/performance1.html 
Altera claims that FLEX10K products are superior to Xilinx XC4085X devices.
Redo part of their experiments and reject or confirm their claims. 
(I haven't done this myself, but you will be needing access to both Xilinx and Altera tools)

4) This is a web page you can get the VPR source code. 
(The tool that was introduced by our guest lecturer, Vaughn Betz on March 10th
http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html
Any reasonable project using VPR is acceptable.

5) Implement various kinds of multipliers (Booth, Baugh-Wooley, etc.) in both
 CPLDs and FPGAs and compare their area-efficiency and speed. 

6)Implement various kinds of multipliers (Booth, Baugh-Wooley, etc.) 
in verious FPGA familiess and compare their area-efficiency and 
speed-performance. Discuss and suggest possible changes (if any) to the 
architecture of FPGAs that improves efficiency of multipliers. 

7) Confirm or reject the claims for the gate capacity of both FPGAs and CPLDs
 from a vendor by calculating the ASIC gate count of a small set of 
benchmark circuits. 
To do this you should use Synopsys to map the circuits to a gate array 
library and get an estimate of the gate count and then compare them with the 
claimed gate counts given in the data sheets. You may make your own benchmark 
circuits or use MCNC benchmarks that are available in EDIF.