University  of  Toronto

Khoman Phang
 

ECE1371 Design Project

  • Due Date:  Monday, March 5th (in class)
  • Description:

    •  
      1. Using an ideal op amp, design a first-order switched-capacitor
      filter circuit with a -3dB frequency of 40kHz using a clock frequency of 1MHz.
      The dc gain is 4 (6dB) and the filter has zero gain at half the clock
      frequency. Include a plot of the frequency response and confirm the circuit
      meets specifications.

      2. Assuming a 0.1% random mismatch in capacitor ratios,
      determine the degree of variability in the 3dB frequency of the filter.

      3. Derive the transfer function of the switched-capacitor filter
      assuming that the op amp now has a finite open loop gain, Ao.
      Through simulations, determine how large Ao must be so that the
      variation in 3dB frequency due to finite gain is no worse than that
      due to capacitor mismatch.