Useful Links

• Ken Shirriff's Implementing FizzBuzz on an FPGA and the sequel Using an FPGA to generate raw VGA video:FizzBuzz with animation are a wonderful, detailed, and nitty-gritty view into his entry into FPGA design where he solves a known problem in straight hardware rather than software.
• Jan Gray's FPGA CPU News (and the predecessor at fpgacpu.org)
• James Hague's programming in the twenty-first century (The sanest computing blog. Read it all, but "Stumbling Into the Cold Expanse of Real Programming" has particular relevance for FPGA system design.)
• Henry Wong's HDLBits provides an interactive tutorial and sandbox for learning Verilog, with on-the-fly simulation and grading.
• Yossi Kreinin's How FPGAs work, and why you'll buy one explains the strengths of FPGAs: architectural flexibility and parallelism where you need it. He doesn't name it as such, but his description of how "instructions" work on FPGAs as opposed to on CPUs is about how the former execute the work more directly rather than interpreting a description of the work itself (i.e.: the software).
• Christian Plessl's FPGA-accelerated High-Performance Computing Close to Breakthrough or Pipedream? and Bringing FPGAs to HPC Production Systems and Codes are specific to HPC, but do a great job of explaining the obstacles to "selling" FPGAs as computing solutions.
• Cliff Cummings' Award-Winning Verilog & SystemVerilog Papers are a goldmine of fundamental and advanced design topics. All are worth reading, even if some are aimed at ASIC tools and/or advocate design styles one could disagree with. For example:
  • Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs and Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog both discuss CDC in great depth. In my experience, CDC is more often than not discussed superficially and gotten wrong in digital design. I have written a smaller introduction to the topic where I also discuss my own mistakes in CDC system design: Basic CDC: Slow → Fast.
  • New Verilog-2001 Techniques for Creating Parameterized Models (or Down With `define and Death of a defparam!) argues well about not using defparam, which has caused me a lot of grief in a commercial design, where it hid a difference in behaviour between simulation and synthesis (and thus in emulation, down the line).
  • SystemVerilog Ports & Data Types For Simple, Efficient and Enhanced HDL Modeling on the other hand, argues for never using `default_nettype none, which I completely disagree with. I find it better to keep code concise to avoid bugs via extensive modularization and re-use, rather than lines-of-code count.
• Avrum Warshawsky of Hardent has posted extensively on the Xilinx Forums (as "avrumw") about CDC and how to properly apply constraints on these cases. Colm Ryan has collected some posts at Avrum's Clock Domain Crossing Widsom.
• dirjud's library of Verilator-compatible Xilinx primitives.