Efficient Multi-Ported Memories for FPGAs

As FPGAs continue to increase in transistor density, designers are using them to build larger and more complex systems-on-chip that require frequent sharing, communication, queueing, and synchronization among distributed functional units and compute nodes. These functions boil down to FIFOs and register files, which can both be implemented using multi-ported memories.

In this work we propose various designs for true multi-ported memories that capitalizes on FPGA block RAMs while providing:

1. substantially better area scaling than a pure logic-based approach
2. higher operating frequencies than the multipumping approach
3. true random access from all ports without contention

We have (so far) explored two major approaches which each use hardware resources differently, but provide identical functionality:

• A form of indirection through a structure called the Live Value Table (LVT), which is itself a small multi-ported memory implemented in reconfigurable logic. Essentially, the LVT coordinates multiple banks of memory into a true multi-ported memory by directing reads to appropriate banks based on which bank holds the most recent or ''live'' write value. The LVT is much narrower than the actual memory banks since it only holds bank numbers rather than full data values, leaving bulk data storage to the Block RAMs.
• A form of data distribution and reconstruction we call XOR-mixing similar to that used in RAID disk arrays. Briefly, we make use of the A XOR B XOR B = A property to spread writes to all memory banks, and use a simple XOR of the output of all banks to reconstruct the original data during reads. XOR-mixing uses more Block RAMs, but less reconfigurable logic, than LVTs for a given memory depth.

People

• Charles Eric LaForest
• Gregory J. Steffan

Publications

• Efficient Multi-Ported Memories for FPGAs
  Charles Eric LaForest and J. Gregory Steffan
  ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2010, Monterey, CA.
  The outcome of my M.A.Sc studies. The paper was very well-received and ranked third in the double-blind review.
  Selected as one of the 25 most significant papers in the first 20 years of the conference: FPGA20 (endorsement)
  Press release from the Dept.: ECE plays major role at FPGA Conference
  Slides: (PPT) (PPTX) (PDF) (ODP)
  (ACM Page)
• Multi-Ported Memories for FPGAs via XOR
  Charles Eric LaForest, Ming G. Liu, Emma Rae Rapati, and J. Gregory Steffan
  ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2012, Monterey, CA.
  Follow-up on the previous paper. Ranked second in the double-blind review.
  Slides: (PPTX)
  (ACM Page)
  

Links

• LVT comp.arch.fpga announcement and discussion

Download

• Example Verilog code for various kinds of multi-ported memories, or grab the tarball.