| Lecture
| Date
| Content
| CO Text
| DL Text
|
| 1
| 8-01-02
| Binary Multipliers
half, full adders (HA,FA)
array multipliers
signed multiplicand M: sign extention of partial products
sign extension tricks (not in text, DL5.6)
signed multiplier Q: booth encoding (radix-2)
| 6.1,6.3-6.4
| 5.6 (prefer CO)
| |
| 2
| 9-01-02
| Booth Encoding (BE)
two's complement
+1 trick: -M = /M + 1, get +1 free using carryin (not in text)
multiplying with BE digits
array multiplier with BE radix-2 (not in text)
radix-4 reduces # of partial products, speeds multiplication
array multiplier cell for BE radix-4 (not in text)
| 6.5
| |
| 3
| 15-01-02
| Fast Multiply
carry-save addition cuts carry propagation
use of fast adders reduces final delay
Wallace tree to reduce depth (delay)
dot-notation to design multipliers
4:2 compressors (not in text)
Booth radix-2 and radix-4 optimizations (not in text)
| 6.5
|
| |
| 4
| 16-01-02
| Logic Function Representation & Minimization
minterms, canonical sum-of-products (SOP) form
truth table, on-set, don't-care set
minimize cost = #inputs + #gates
minimization strategy: K-map
literal, implicant, prime implicant, essential prime implicant
cover, irredundant cover, minimum cover
|
| reviewed 2.6, 4.1, 4.2
you should know
4.4-4.7
| |
| 5
| 22-01-02
| Minimization, Cubical Notation
minimization strategy: branching heuristic
0-cubes, 1-cubes, 2-cubes
1D, 2D, 3D, 4D cubes
maximize size of cube: vertex, edges, faces, and cubes
extension to 5D++ hard to visualize, but easy for software
|
| 4.2, 4.9
| |
| 6
| 23-01-02
| *-Operation (star-operation)
can be used by software
generates implicants from a cover (eg, all minterms)
generated implicants can be smaller or larger cubes
finds all implicants
algorithm for generating all prime implicants
|
| 4.10.1
| |
| 7
| 29-01-02
| Finite State Machines
example: set output z=1 if input w high for >= 2 cycles
Moore model: outputs f(state-only) labeled in state bubbles
Mealy model: outputs f(state,inputs) labeled on edges
start with FSM bubble diagram
5 design steps: state table, state assignment, state-assigned table, optimize logic functions, timing diagram
setup, hold, clock-to-output delays
Mealy more susceptible to glitches (uncontrollable inputs)
Moore has fewer glitches (but still present!)
Moore: more states. outputs come 1 cycle later.
|
| 8.1, 8.2
| |
| 8
| 30-01-02
| Finite State Machines
Mealy/Moore differences
example: bit serial adder
start with Mealy FSM (2 states)
derive Moore FSM (4 states) by splitting Mealy states
Moore FSM must have at least one state per unique output value
here, easy Moore FSM was found through clever design (eg, via state assignment)
easy Moore FSM: place FF on outputs of Mealy FSM
other Moore FSMs possible (eg, different state assignment)
Moore: outputs come 1 cycle later. are design specs met?
|
| 8.4 (VHDL for labs), 8.5
| |
| 9
| 05-02-02
| Bus Arbiter FSM, Algorithmic State Machine (ASM) Charts
only one bus master at a time
arbiter designates bus master
bus protocol: simple priority scheme (bad: starvation)
device protocol: request bus, wait for grant, use it, release request
bus timing, one master, edges arrive in order
dead cycle between masters (idle)
ASM: describes digital system
state box (Moore outputs)
decision box (eg, edges in FSM)
conditional output box (Mealy outputs), always follows decision box
more ASM examples (Moore, Mealy)
|
| 8.8, 8.10
| |
| 10
| 06-02-02
| Algorithmic State Machine (ASM) Charts
example: bit counting
implied timing in ASM charts can be confusing (note state S2 outputs)
extracting datapath, control circuits
sample VHDL code: bitcount.vhd
|
| 10.1, 10.2.1
| |
| 11
| 12-02-02
| Multi-cycle Multiplier
Russian Peasant Algorithm
ASM similar to bitcounting
datapath width 2n
optimization 1: use adder of width n
above optimization requires shift-right reg for P
optimization 2: use lower half of P to hold B (=Q)
|
| 10.2.3
| |
| 12
| 12-02-02
| Multi-cycle Divider
long-hand binary division
A=dividend, B=divisor
Q=quotient=A/B, R=remainder=A%B
datapath uses R||A (R in parallel with A) shift-left reg
shift-left reg to generate quotient Q
ASM chart uses 2 cycles per iteration (bit in Q)
optimization 1: combine states, 1 cycle per iteration
above optimization introduces problem, need extra R bit
optimization 2: (not covered) store Q in A.
|
| 10.2.4
| |
| 13
| 12-02-02
| I/O and Bus Design
simple asynchronous bus design
master-ready/slave-ready full handshake
sharing bus wires: open collector, open drain, tristate control
parallel input port (keyboard)
parallel output port (printer)
| 4.5, 4.6.1
|
| |
| 14
| 13-02-02
| Bus Design
many bus designs, different goals (cheap, simple, high performance)
recent trend: serial bus, cheap and high-speed signalling technology
68000 Bus
68000 asynchronous, but internal processor clock synchronizes changes
68000 bus read cycle
68000 bus write cycle
slave use of /DTACK to delay read response (or acceptance of writes)
/LDS, /UDS signals, 32-bit transfers
note you will need to know DMA for future lab
UltraGizmo lab book
pages 61-62, 71-73.
68306 User Manual
3.1, 3.7-3.8
see also sections 3.2-3.3 for DMA
| |
| 15
| 05-03-02
| Timing and Delays
gate the data, not the clock
glitches in clock are catastrophic
treat sub-circuits as black boxes
black boxes specify: i/o, function, timing parameters
timing parameters: setup time, hold time, clock-to-output, max clock speed Fmax
violate setup/hold: metastability
coping with metastability using double flip-flops
fixing setup violations (reduce logic delays, lower Fmax, move FF closer to inputs)
fixing hold violations (increase logic delays, move FF farther to inputs)
- Note: cannot fix hold violations by changing clock frequency
- fix hold violations first, then setup violations
backwards-routed clocks, H-tree clocks
| 10.3
| |
| MIDTERM MATERIAL ENDS HERE. |
| 16
| 06-03-02
| Timing Hazards
two types: static and dynamic hazards
two static hazards:
o static-1 hazard occurs in SOP logic (AND/OR, NAND/NAND),
o static-0 hazard occurs in POS logic (OR/AND, NOR/NOR)
two dynamic hazards:
o dynamic-0-to-1 hazard
o dynamic-1-to-0 hazard
o occurs in multilevel logic
o multiple paths (delays) from an input to output
o does not occur in SOP or POS logic
static and dynamic hazard examples
o static hazards arise from A and !A inputs in SOP/POS
o dynamic hazards arise from embedded static hazards
fixing static and dynamic hazards
o fix static hazards by covering transitions
o cover transitions using consensus terms (redundant terms)
o is fixing embedded hazards sufficient to fix all dynamic hazards?
| 9.6
| |
| 17
| 12-03-02
| MIDTERM REVIEW |
| 18
| 13-03-02
| Asynchronous Sequential Circuits
sequential circuits
- past input sequence influences current/future events
- past summarized by current state (memory)
- synchronous: use common clock signal, eg memory from FFs
- asynchronous: no clock, memory from logic feedback and delay
fundamental mode: assume only one async input changes at a time
stable states
flow table, excitation table
avoid hazards in logic
| 9.1, 9.2
| |
| 19
| 19-03-02
| Asynchronous FSMs
design flow
- state diagram
- flow table (new concepts)
- state assignment (new concepts)
- excitation table
- next-state and output logic expressions
- draw circuit
parity generator, Moore FSM example
state assignment
- one state bit changes at a time
- embed state assignment on cube
race condition occurs if:
- 2 or more inputs change
- outcome is different depending which changes first
| 9.3
| |
| 20
| 20-03-02
| Asynchronous FSMs
bus arbiter example
state assignment difficulty
- cannot always embed onto cube
- cannot always cope with race conditions
- flow through existing states
- add new states
| 9.3
| |
| 21
| 26-03-02
| Asynchronous State Assignment
one-hot state assignment always works, inefficient
another state assignment strategy:
- relabel flow table with transitions
- draw transition diagram
- guess state assignment
- fix problem transitions (diagonals)
- repeat as necessary
relabled flow table
- enumerate (#) each stable state
- relabel each column with destination stable state #
transition diagram
- one vertex for each row (label with state)
- edge between two vertices if same # in any column
- label edge with # from column
- underline label if both ends are unstable
- underlined labels: unnecessary transitions
guess state assignment
- can re-use or ignore unnecessary transitions
- introduce new states on unlabeled vertices of cube
- map all transitions to edges in cube
- add new state variables (bits) if necessary
| 9.5
| |
| 22
| 27-03-02
| State Minimization: Partitioning
two steps: partitioning, merging
partitioning
- place all states in one group, P1
- divide P1 into groups, each has unique output value, P2
- divide P2 into groups based on successor states, P3
- continue last step until Pn = Pn-1
| 8.6,9.4
| |
| 23
| 2-04-02
| State Minimization: Merging
merging uses unspecified entries to reduce
compatible states can be merged
two states are next-state compatible if:
- every column has same entry, OR
- every column has one/both entries unspecified, OR
- every column has stable entry
two states are output compatible if:
- (Moore) outputs are compatible
- (Mealy) outputs are compatible in only stable states
can merge if both next-state compatible and output compatible
merger diagram:
- one vertex per state
- add edge if two states can be merged
- merge cliques to produce fewest # of groups
- redraw flow table
- repeat until no more merging can be done
Mealy outputs
- same output as Moore in stable states
- most unstable states are "don't care", BUT...
- outputs must be glitch free during transitions
- force output on transitions between stable states if:
- force 0 output if stable states both output 0
- force 1 output if states both output 1
- don't care output on other transitions, ie between stable states with different outputs
| 9.4
| |
| 24
| 03-04-02
| Testing Combinational Logic
assume only single faults exist
assume stuck-at fault model
find a test input
- should produce output f
- if fault under test exists, test input must produce output not(f)
- producing not(f) is how we detect the fault
find a test set, number of test inputs to test all faults
path sensitizing to detect faults along path
consistency check determines inputs that sensitize a path
fault propagation detects specific faults
| 11.1,11.2,11.3
| |
| 25
| 09-04-02
| Logic Minimization: #-Operation
C = A # B, sharp-operation. think: C = A remove B
C is the part of A not covered by B
C may contain 0, 1, or more cubes
3 cases for C:
- A and B disjoint, C = A (one or more "phi" in Ai#Bi)
- A covered entirely by B, C = empty set (all "epsilon" in Ai#Bi)
- A partially covered by B, C = one or more cubes
in third case, each cube in C is found by changing A:
- find position i where digit Ai=x and Bi=0 or 1.
- replace digit Ai with digit not(Bi)
let P1 be essential PI, let P be set of all PIs:
P1 is essential if P1 # (P - P1) # DC produces any cubes
| 4.10
| |
| 26
| 10-04-02
| EXAM REVIEW
Some Y2000 Exam Solutions
For Question 2b of Y2000 exam,
Haresh Khemani gives this solution.
|
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