Publications

• S. Brown, G. Lemieux, and M. Khellah, ``Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays'' (PDF), Journal of VLSI Design, 4(4), pp. 275 - 291, 1996.

• G. Lemieux, D. Lewis, ``Analytical Framework for Switch Block Design'' (PDF), Field-Programmable Logic and Applications, La Grande Motte, France, pp. 122 - 131, September 2002.
  Warning: the above paper was formatted for an A4 page size.
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• G. Lemieux, D. Lewis, ``Circuit Design of FPGA Routing Switches'' (PDF), ACM/SIGDA International Symposium on FPGAs, Monterey, CA, pp. 19 - 28, February 2002.
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• G. Lemieux, D. Lewis, ``Using Sparse Crossbars within LUT Clusters'' (PDF), ACM/SIGDA International Symposium on FPGAs, Monterey, CA, pp. 59 - 68, February 2001.
  
  
• G. Lemieux, P. Leventis, D. Lewis, ``Generating Highly-Routable Sparse Crossbars for PLDs'' (PDF), ACM/SIGDA International Symposium on FPGAs, Monterey, CA, pp. 155 - 164, February 2000.
  
  
• R. Grindley, T. Abdelrahman, S. Brown, S. Caranci, D. DeVries, B. Gamsa, A. Grbic, M. Gusat, R. Ho, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, P. McHardy, S. Srbljic, M. Stumm, Z. Vranesic, and Z. Zilic ``The NUMAchine Multiprocessor'' (PDF), International Conference on Parallel Processing, pages 487-496, Toronto, Canada, August 21-24, 2000.
  
  
• A. Grbic, S. Brown, S. Caranci, R. Grindley, M. Gusat, G. Lemieux, K. Loveless, N. Manjikian, S. Srbljic, M. Stumm, Z. Vranesic, and Z. Zilic ``Design and Implementation of the NUMAchine Multiprocessor'' (PDF), Proceedings of the 35th IEEE Design Automation Conference, San Francisco, CA, June 1998.
  
  
• G. Lemieux, S. Brown, D. Vranesic, ``On Two-Step Routing for FPGAs'' (PDF), International Symposium on Physical Design, Napa, CA, pp. 60 - 66, April 1997.
  
  

• G. Lemieux, D. Lewis, ``Checkerboard Switch Block Topologies for Routing Diversity'' poster session at ACM/SIGDA International Symposium on FPGAs, Monterey, CA, February 2002.
  poster presentation html, PDF
  
  
• G. Lemieux, S. Caranci, R. Grindley, and K. Loveless, ``NUMAchine Global Ring Hardware Design'', PDF March 2001.
  
  
• Z. Vranesic, S. Brown, M. Stumm, S. Caranci, A. Grbic, R. Grindley, M. Gusat, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, T. Abdelrahman, B. Gamsa, P. Pereira, K. Sevcik, A. Elkateeb, and S. Srbljic, ``The NUMAchine Multiprocessor'', CSRI Technical Report CSRI-324 (other options), Computer Systems Research Institute, University of Toronto, June 1995.
  
  
• Z. Zilic, G. Lemieux, K. Loveless, S. Brown, and Z. Vranesic ``Designing for High Speed-Performance in CPLDs and FPGAs'' (PDF), Proc. 3rd Canadian Workshop on Field-Programable Devices (FPD'95): Technology, Tools, and Applications, Montreal, Canada, pp. 108 - 113, May 1995.
  
  
• G. Lemieux and S. Brown, ``A Detailed Router for Allocating Wire Segments in FPGAs'' (PDF), ACM Physical Design Workshop, Lake Arrowhead, California, pp. 215 - 226, April 1993.
  
  

• G. Lemieux, ``Hardware Performance Monitoring in Multiprocessors'', M.A.Sc. Thesis, University of Toronto, January 1996. (144k compressed postscript, 219k PDF, other options)
  
  
• G. Lemieux, ``Design and Implementation of Detailed Router Software for Segmented-Architecture Field-Programmable Gate Arrays'' (PDF), B.A.Sc. Thesis, University of Toronto, April 1993.